Xilinx Virtex-6 Libraries Guide for HDL Designs
Xilinx Virtex-6 Libraries Guide for HDL Designs
Xilinx Virtex-6 Libraries Guide for HDL Designs
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Chapter 4: About Design ElementsV<strong>HDL</strong> Instantiation TemplateUnless they already exist, copy the following two statements and paste them be<strong>for</strong>e the entity declaration.Library UNISIM;use UNISIM.vcomponents.all;-- IBUFDS: Differential Input Buffer-- Spartan-3/3E/3A-- <strong>Xilinx</strong> <strong>HDL</strong> <strong>Libraries</strong> <strong>Guide</strong>, version 11.2IBUFDS_inst : IBUFDSgeneric map (CAPACITANCE => "DONT_CARE", -- "LOW", "NORMAL", "DONT_CARE" (<strong>Virtex</strong>-4 only)DIFF_TERM => FALSE, -- Differential Termination (<strong>Virtex</strong>-4/5, Spartan-3E/3A)IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay <strong>for</strong> buffer,-- "0"-"12" (Spartan-3E)-- "0"-"16" (Spartan-3A)IFD_DELAY_VALUE => "AUTO", -- Specify the amount of added delay <strong>for</strong> input register,-- "AUTO", "0"-"6" (Spartan-3E)-- "AUTO", "0"-"8" (Spartan-3A)IOSTANDARD => "DEFAULT")port map (O => O, -- Clock buffer outputI => I, -- Diff_p clock buffer input (connect directly to top-level port)IB => IB -- Diff_n clock buffer input (connect directly to top-level port));-- End of IBUFDS_inst instantiationVerilog Instantiation Template// IBUFDS: Differential Input Buffer// <strong>Virtex</strong>-4/5, Spartan-3/3E/3A// <strong>Xilinx</strong> <strong>HDL</strong> <strong>Libraries</strong> <strong>Guide</strong>, version 11.2IBUFDS #(.CAPACITANCE("DONT_CARE"), // "LOW", "NORMAL", "DONT_CARE" (<strong>Virtex</strong>-4 only).DIFF_TERM("FALSE"), // Differential Termination (<strong>Virtex</strong>-4/5, Spartan-3E/3A).IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay <strong>for</strong>// the buffer: "0"-"12" (Spartan-3E)// "0"-"16" (Spartan-3A).IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay <strong>for</strong> input// register: "AUTO", "0"-"6" (Spartan-3E)// "AUTO", "0"-"8" (Spartan-3A).IOSTANDARD("DEFAULT") // Specify the input I/O standard) IBUFDS_inst (.O(O), // Buffer output.I(I), // Diff_p buffer input (connect directly to top-level port).IB(IB) // Diff_n buffer input (connect directly to top-level port));// End of IBUFDS_inst instantiationFor More In<strong>for</strong>mationSee the <strong>Virtex</strong>-6 FPGA User Documentation (User <strong>Guide</strong>s and Data Sheets).<strong>Virtex</strong>-6 <strong>Libraries</strong> <strong>Guide</strong> <strong>for</strong> <strong>HDL</strong> <strong>Designs</strong>UG623 (v 11.4) December 2, 2009 www.xilinx.com 155
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