Chapter 4 Introduction
Chapter 4 Introduction
Chapter 4 Introduction
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Morgan Kaufmann Publishers 31 January 2013Datapath With Jumps AddedPerformance Issuesn Longest delay determines clock periodn Critical path: load instructionn Instruction memory → register file → ALU →data memory → register filen Not feasible to vary periodfor different instructionsn Violates design principlen Making the common case fastn We will improve performance by pipeliningCSE 420 <strong>Chapter</strong> 4 — The Processor — 30
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