Chapter 4 Introduction

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Morgan Kaufmann Publishers 31 January 2013Exception ExampleCSE 420 Chapter 4 — The Processor — 103Multiple Exceptionsn Pipelining overlaps multiple instructionsn Could have multiple exceptions at oncen Simple approach:deal with exception from earliest instructionnnFlush subsequent instructions“Precise” exceptionsn In complex pipelinesn Multiple instructions issued per cyclennOut-of-order completionMaintaining precise exceptions is difficult!CSE 420 Chapter 4 — The Processor — 104
Morgan Kaufmann Publishers 31 January 2013Imprecise Exceptionsn Just stop pipeline and save staten Including exception cause(s)n Let the handler work it outn Which instruction(s) had exceptionsnWhich to complete or flushn May require “manual” completionn Simplifies hardware,but more complex handler softwaren Not feasible for complex, multiple-issue,out-of-order pipelinesCSE 420 Chapter 4 — The Processor — 105Instruction-Level Parallelism (ILP)n Pipelining: executing multiple instructions inparalleln To better utilize ILPn Deeper pipelinenn Less work per stage ⇒ shorter clock cycleMultiple issuen Replicate pipeline stages ⇒ multiple pipelinesn Start multiple instructions per clock cyclen CPI < 1, so use Instructions Per Cycle (IPC)n E.g., 4GHz 4-way multiple-issuen 16 BIPS, peak CPI = 0.25, peak IPC = 4n But dependencies reduce this in practice§4.10 Parallelism and Advanced Instruction Level ParallelismCSE 420 Chapter 4 — The Processor — 106
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Chapter 4 Introduction

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