Chapter 4 Introduction
Chapter 4 Introduction
Chapter 4 Introduction
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Morgan Kaufmann Publishers 31 January 2013Pipeline Performancen Assume time for stages isn 100ps for register read or writen200ps for other stagesn Compare pipelined datapath with single-cycledatapathInstrInstr fetch RegisterreadALU opMemoryaccessRegisterwriteTotal timelw 200ps 100 ps 200ps 200ps 100 ps 800pssw 200ps 100 ps 200ps 200ps 700psR-format 200ps 100 ps 200ps 100 ps 600psbeq 200ps 100 ps 200ps 500psCSE 420 <strong>Chapter</strong> 4 — The Processor — 33Pipeline PerformanceSingle-cycle (T c = 800ps)Pipelined (T c = 200ps)CSE 420 <strong>Chapter</strong> 4 — The Processor — 34
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