Chapter 4 Introduction

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Morgan Kaufmann Publishers 31 January 2013The Opteron X4 Microarchitecture72 physicalregisters§4.11 Real Stuff: The AMD Opteron X4 (Barcelona) PipelineCSE 420 Chapter 4 — The Processor — 127The Opteron X4 Pipeline Flown For integer operationsnnFP is 5 stages longerUp to 106 RISC-ops in progressn Bottlenecksn Complex instructions with long dependenciesnnBranch mispredictionsMemory access delaysCSE 420 Chapter 4 — The Processor — 128
Morgan Kaufmann Publishers 31 January 2013Fallaciesn Pipelining is easy (!)n The basic idea is easynThe devil is in the detailsn e.g., detecting data hazardsn Pipelining is independent of technologyn So why haven’t we always done pipelining?nnMore transistors make more advanced techniquesfeasiblePipeline-related ISA design needs to take account oftechnology trendsn e.g., predicated instructions§4.13 Fallacies and PitfallsCSE 420 Chapter 4 — The Processor — 129Pitfallsn Poor ISA design can make pipelininghardern e.g., complex instruction sets (VAX, IA-32)n Significant overhead to make pipelining workn IA-32 micro-op approachn e.g., complex addressing modesn Register update side effects, memory indirectionn e.g., delayed branchesn Advanced pipelines have long delay slotsCSE 420 Chapter 4 — The Processor — 130
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Chapter 4 Introduction

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