Chapter 4 Introduction

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Morgan Kaufmann Publishers 31 January 2013Dynamic Multiple Issuen “Superscalar” processorsn CPU decides whether to issue 0, 1, 2, …each cyclen Avoiding structural and data hazardsn Avoids the need for compiler schedulingn Though it may still helpn Code semantics ensured by the CPUCSE 420 Chapter 4 — The Processor — 119Dynamic Pipeline Schedulingn Allow the CPU to execute instructionsout of order to avoid stallsn But commit result to registers in ordern Examplelw $t0, 20($s2)addu $t1, $t0, $t2sub $s4, $s4, $t3slti $t5, $s4, 20n Can start sub while addu is waiting for lwCSE 420 Chapter 4 — The Processor — 120
Morgan Kaufmann Publishers 31 January 2013Dynamically Scheduled CPUPreservesdependenciesHold pendingoperandsResults also sentto any waitingreservation stationsReorders buffer forregister writesCan supplyoperands forissued instructionsCSE 420 Chapter 4 — The Processor — 121Register Renamingn Reservation stations and reorder buffereffectively provide register renamingn On instruction issue to reservation stationn If operand is available in register fileor reorder buffer,n Copied to reservation stationn No longer required in the registerso it can be overwrittenn If operand is not yet available,n It will be provided to the reservation stationby a function unitn Register update may not be requiredCSE 420 Chapter 4 — The Processor — 122
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Chapter 4 Introduction

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