Chapter 4 Introduction

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Morgan Kaufmann Publishers 31 January 2013Pipeline Speedupn If all stages are balancedn i.e., all take the same timen Time between instructions pipelined= Time between instructions nonpipelinedNumber of stagesn If not balanced, speedup is lessn Speedup is due to increased throughputn Latency (time for each instruction)does not decreaseCSE 420 Chapter 4 — The Processor — 35Pipelining and ISA Designn MIPS ISA designed for pipeliningn All instructions are 32-bitsn Easier to fetch and decode in one cyclen c.f. x86: 1- to 17-byte instructionsn Few and regular instruction formatsn Can decode and read registers in one stepn Load/store addressingn Can calculate address in 3 rd stage,access memory in 4 th stagen Alignment of memory operandsn Memory access takes only one cycleCSE 420 Chapter 4 — The Processor — 36
Morgan Kaufmann Publishers 31 January 2013Hazardsn Situations that prevent starting the nextinstruction in the next cyclen Structural hazardn A required resource is busyn Data hazardn Need to wait for previous instructionto complete its data read/writen Control hazardn Deciding on control actiondepends on previous instructionCSE 420 Chapter 4 — The Processor — 37Structure Hazardsn Conflict for use of a resourcen In MIPS pipeline with a single memoryn Load/store requires data accessn Instruction fetch would have to stallfor that cyclen Would cause a pipeline “bubble”n Hence, pipelined data paths requireseparate instruction & data memoriesn so separate instruction & data cachesCSE 420 Chapter 4 — The Processor — 38
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Chapter 4 Introduction

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