NAND Flash Memory MT29F4G08AAAWP ... - Micron

4Gb, 8Gb, and 16Gb x8 NAND Flash MemoryArray OrganizationFigure 7:Array Organization for MT29F8G08BAA and MT29F16G08FAA (x8)Die 0 Die 1Cache Register2,0482,112 bytes642,0482,112 bytes642,0482,112 bytes642,0482,112 bytes64I/O0I/O7Data Register2,048 642,048642,048 642,048641 page = (2K + 64 bytes)2,048 blocksper plane4,096 blocksper die1 block 1 block1 block 1 block1 block = (2K + 64) bytes x 64 pages= (128K + 4K) bytes1 plane = (128K + 4K) bytes x 2,048 blocks= 2,112Mb1 die = 2,112Mb x 2 planes= 4,224MbPlane 0: evennumberedblocks numbered blocksPlane 1: odd-(0, 2, 4, 6, ..., (1, 3, 5, 7, ...,4,092, 4,094) 1 4,093, 4,095)Plane 0: evennumberedblocks(4,096, 4,098, ...,8,188, 8,190)Plane 1: oddnumberedblocks(4,097,4,099, ...,8,189, 8,191)1 device = 4,224Mb x 2 die= 8,448MbNotes: 1. Die 0, Plane 0: BA18 = 0; BA6 = 0.Die 0, Plane 1: BA18 = 0; BA6 = 1.Die 1, Plane 0: BA18 = 1; BA6 = 0.Die 1, Plane 1: BA18 = 1; BA6 = 1.2. For the 16Gb MT29F16G08FAA, the 8Gb array organization shown here applies to each chipenable (CE# and CE2#).Table 4:Array Addressing: MT28F8G08BAA and MT29F16G08FAACycle I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0First CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0Second LOW LOW LOW LOW CA11 CA10 CA9 CA8Third BA7 BA6 PA5 PA4 PA3 PA2 PA1 PA0Fourth BA15 BA14 BA13 BA12 BA11 BA10 BA9 BA8Fifth LOW LOW LOW LOW LOW BA18 3 BA17 BA16Notes:1. CAx = column address; PAx = page address; BAx = block address.2. If CA11 is 1, then CA[10:6] must be “0.”3. Die address boundary: 0 = 0–4Gb; 1 = 4Gb–8Gb.PDF: 09005aef81b80e13/Source: 09005aef81b80eacMicron Technology, Inc., reserves the right to change products or specifications without notice.4gb_nand_m40a__2.fm - Rev. B 2/07 EN 14 ©2006 Micron Technology, Inc. All rights reserved.