NAND Flash Memory MT29F4G08AAAWP ... - Micron

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4Gb, 8Gb, and 16Gb x8 NAND Flash MemoryCommand DefinitionsFigure 31:TWO-PLANE INTERNAL DATA MOVE Operationt Rt DBSYR/B#I/Ox 00h Address (5 cycles) 00hAddress (5 cycles)35h85hAddress (5 cycles)11h1st-plane source2nd-plane source1st-plane destination1t PROGR/B#I/Ox80hAddress (5 cycles)10h70hStatus(or 81h)2nd-plane destination1Figure 32:TWO-PLANE INTERNAL DATA MOVE Operation with RANDOM DATA INPUTtRR/B#I/Ox 00h Address (5 cycles) 00hAddress (5 cycles)35h85h Address (5 cycles) Data 85h Address (2 cycles) Data11h1st-plane source 2nd-plane source1st-plane destination Optionalt DBSY t PROGUnlimited numberof repetitions1R/B#I/Ox80hAddress (5 cycles)Data85h Address (2 cycles) Data 10h 70h Status(or 81h) 2nd-plane destination OptionalUnlimited numberof repetitions1PDF: 09005aef81b80e13/Source: 09005aef81b80eacMicron Technology, Inc., reserves the right to change products or specifications without notice.4gb_nand_m40a__2.fm - Rev. B 2/07 EN 44 ©2006 Micron Technology, Inc. All rights reserved.
4Gb, 8Gb, and 16Gb x8 NAND Flash MemoryCommand DefinitionsTWO-PLANE BLOCK ERASE 60h-60h-D0hThe TWO-PLANE BLOCK ERASE (60h-60h-D0h) operation is similar to the BLOCKERASE (60h-D0h) operation. It erases two blocks instead of one. The blocks to be erasedmust be on different planes on the same die. The first-plane and second-planeaddresses must meet the two-plane addressing requirements (see “Two-PlaneAddressing” on page 35). Additionally, the page addresses, PA[5:0], for both planes mustbe LOW.Begin a TWO-PLANE BLOCK ERASE operation by writing 60h to the command register,followed by 3 ADDRESS cycles of the first-plane block address. Then write 60h again tothe command register, followed by 3 ADDRESS cycles of the second-plane blockaddress. Finally, issue the D0h command.R/B# goes LOW for the duration of block erase time, t BERS. When block erasure iscomplete, R/B# returns HIGH. The READ STATUS (70h) command also indicates thatthe device is ready when status register bit 6 is set to “1.” The only valid commandsduring t BERS are READ STATUS (70h), TWO-PLANE/MULTIPLE-DIE READ STATUS(78h), and RESET (FFh).If the READ STATUS (70h) command indicates an error in the operation (status registerbit 0 = 1), then use the TWO-PLANE/MULTIPLE-DIE READ STATUS (78h) commandtwice—once for each plane—to determine which plane operation failed.Figure 33:TWO-PLANE BLOCK ERASE OperationCLECE#WE#ALEt BERSR/B#RE#I/Ox 60h Address input (3 cycles) 60h Address input (3 cycles) D0h70h Status1st plane2nd planeI/O 0 = 0 ERASE successfulI/O 0 = 1 ERASE errorDon’t CarePDF: 09005aef81b80e13/Source: 09005aef81b80eacMicron Technology, Inc., reserves the right to change products or specifications without notice.4gb_nand_m40a__2.fm - Rev. B 2/07 EN 45 ©2006 Micron Technology, Inc. All rights reserved.
Page 1 and 2: 4Gb, 8Gb, and 16Gb x8 NAND Flash Me
Page 4: 4Gb, 8Gb, and 16Gb x8 NAND Flash Me
Page 7 and 8: List of Tables4Gb, 8Gb, and 16Gb x8
Page 47 and 48: Interleaved Die Operations4Gb, 8Gb,
Page 55 and 56: PDF: 09005aef81b80e13/Source: 09005
Page 57 and 58: WRITE PROTECT Operation4Gb, 8Gb, an
Page 59 and 60: Electrical Characteristics4Gb, 8Gb,

NAND Flash Memory MT29F4G08AAAWP ... - Micron

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