Commonly Used Metrics for Performance Analysis - Power.org

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Metrics for Performance Analysis7 Memory BandwidthThis chapter lists and describes the events, metrics and groups needed for calculating the average memorybandwidth used by application. This is often a critical limiting factor to application performance. An accuratemeasure of memory bandwidth involves a much more detailed monitoring of events across the entire memoryfabric of the node; this method, though relatively simple to implement, is less accurate. When an applicationhas a lot of “interventions” (data from any other on-chip cache), this process will over-estimate memorybandwidth.The instrumentation used to collect memory bandwidth events exists in the memory controller synchronousinterface to the Powerbus. It is not associated with any particular core. Any statistics collected are anaggregate of all the off-chip memory requests from all the cores on the chip. Requests are in units of thecache line, 128 bytes. Note that these events exclude any requests that are satisfied by any of the POWER7caches.A typical POWER7 chip has either 1 or 2 memory controllers (MCs) and the first is always measured. Wherethere are 2 MCs, the event counts of the first should be closely mirrored by the second, because which one isused to satisfy a memory access request is determined by the parity of the number of the cache linerequested.7.1Descriptions of EventsPM_MEM0_RQ_DISP7.2 MetricsThe memory controller has dispatched a read operation fromthe Powerbus.The memory controller fetches a 128-byte cacheline from the DIMMs and returns the data to the Powerbus.This event is incremented by all reads seen by this memory controller, so it is a sum of the reads from allthreads on this chip which reference local physical memory and threads on adjacent chips that also accessthis chip’s local memory (which they classify as “remote” memory reads).PM_MEM0_WQ_DISPThe memory controller has dispatched a write operation fromthe Powerbus ,The memory controller writes a 128-byte cacheline to the DIMMs. This event is incremented by all writesseen by this memory controller, so it is a sum of the writes from all threads on this chip which referenced localphysical memory and threads on adjacent chips that also access this chip’s local memory (which they classifyas “remote” memory writes).PM_RUN_CYCRun_cyclesProcessor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doinguseful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idleloop.The events above are routed from the memory controller across multiple asynchronous clock domains to thethread level PMUs, so to prevent signal loss the counts need to be scaled appropriately. For a single MC:Read_BW (GB/s)Read Bandwidth in gigabytes/secFormula: (cacheline_size * fixed_prescalar * ( ReadQ dispatches )) / 1e9/ secs= ( 128 * 8 * (PM_MEM0_RQ_DISP)) / 1e9/ secsWrite_BW (GB/s)Write Bandwidth in gigabytes/secFormula: (cacheline_size * fixed_prescalar * ( WriteQ dispatches )) / 1e9/ secs= ( 128 * 8 * (PM_MEM0_WQ_DISP)) / 1e9/ secs“secs” is the number of elapsed seconds during which the events were counted. This is equivalent to usingCopyright ©2011 IBM Corporation Page 24 of 52
Metrics for Performance AnalysisPM_RUN_CYC/[machine clock speed]If a POWER7 chip uses two controllers, multiply these rates by two.7.3 Event GroupsOnly 1 group is needed: pm_nest5.Table 7-1 Memory bandwidth events with their corresponding event group and brief descriptionEvent Name Group Name Event DescriptionPM_MEM0_RQ_DISPpm_nest5Nest events (MC0/MC1/PB/GX),Pair0 Bit1PM_MEM0_RQ_DISPpm_nest5Nest events (MC0/MC1/PB/GX),Pair3 Bit1PM_RUN_CYC pm_nest5 Run cyclesCopyright ©2011 IBM Corporation Page 25 of 52
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Commonly Used Metrics for Performance Analysis - Power.org

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