Commonly Used Metrics for Performance Analysis - Power.org

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Metrics for Performance Analysis13 Instruction StatisticsThis chapter lists and describes the events, metrics and groups needed to characterize how efficientlyinstructions are fetched.13.1 Descriptions of EventsThere are 15 events, distributed across 6 event groups, needed for these POWER7 instruction statistics.This section provides more details on each event and how it is triggered.PM_IC_PREF_WRITEInstruction prefetch written into IL1Count of instruction prefetch sectors written in the L1. Writes are always written as LRU and subsequent readmakes it MRUPM_INST_FROM_DL2L3_MODInstruction fetched from distant L2 or L3 modifiedThe processor's Instruction Cache was reloaded with Modified (M) data from a chip's L2 or L3 on a differentNode (Distant) due to a demand load .PM_INST_FROM_DL2L3_SHRInstruction fetched from distant L2 or L3 sharedThe processor's Instruction Cache was reloaded with Shared (S) data from a chip's L2 or L3 on a differentNode (Distant) due to a demand load .PM_INST_FROM_DMEMInstruction fetched from distant memoryThe processor's Instruction Cache was reloaded with data from a chip's memory on a different Node(Distant) due to a demand load .PM_INST_FROM_L2Instruction fetched from L2The processor's Instruction Cache was reloaded with data from the local chiplet's L2 cache due to a demandload.PM_INST_FROM_L21_MODInstruction fetched from another L2 on same chip modifiedThe processor's Instruction Cache was reloaded with Modified (M) data from another L2 on the same chipdue to a demand load .PM_INST_FROM_L21_SHRInstruction fetched from another L2 on same chip sharedThe processor's Instruction Cache was reloaded with Shared (S) data from another L2 on the same chipdue to a demand load .PM_INST_FROM_L3Instruction fetched from L3The processor's Instruction Cache was reloaded with data from the local chiplet's L3 cache due to a demandload.PM_INST_FROM_L31_MODInstruction fetched from another L3 on same chip modifiedThe processor's Instruction Cache was reloaded with Modified (M) data from another L3 on the same chipdue to a demand load .PM_INST_FROM_L31_SHRInstruction fetched from another L3 on same chip sharedThe processor's Instruction Cache was reloaded with Shared (S) data from another L3 on the same chipdue to a demand load .PM_INST_FROM_LMEMInstruction fetched from local memoryThe processor's Instruction Cache was reloaded with data from the local chip's memory due to a demandload.PM_INST_FROM_RL2L3_MODInstruction fetched from remote L2 or L3 modifiedCopyright ©2011 IBM Corporation Page 40 of 52
Metrics for Performance AnalysisThe processor's Instruction Cache was reloaded with Modified (M) data from a chip's L2 or L3 on the sameNode (Remote) due to a demand load .PM_INST_FROM_RL2L3_SHRInstruction fetched from remote L2 or L3 sharedThe processor's Instruction Cache was reloaded with Shared (S) data from a chip's L2 or L3 on the sameNode (Remote) due to a demand load .PM_INST_FROM_RMEMInstruction fetched from remote memoryThe processor's Instruction Cache was reloaded with data from another chip's memory on the same nodedue to a demand load.PM_L1_ICACHE_MISSDemand iCache MissAn instruction fetch missed the L1 Instruction cache13.2 MetricsInstruction usage is characterized with the following metrics:ICACHE_PREF(%)% of ICache reloads due to prefetchFormula: PM_IC_PREF_WRITE * 100 / PM_L1_ICACHE_MISSICache_MISS_RELOADIcache Fetchs per Icache MissFormula: PM_L1_ICACHE_MISS - PM_IC_PREF_WRITE) / PM_L1_ICACHE_MISSINST_FROM_L2(%)% of ICache reloads from L2Formula: PM_INST_FROM_L2 * 100 / PM_L1_ICACHE_MISSINST_FROM_L21_MOD(%)% of ICache reloads from Private L2, other coreFormula: PM_INST_FROM_L21_MOD * 100 / PM_L1_ICACHE_MISSINST_FROM_L21_SHR(%)% of ICache reloads from Private L2, other coreFormula: PM_INST_FROM_L21_SHR * 100 / PM_L1_ICACHE_MISSINST_FROM_L31_MOD(%)% of ICache reloads from Private L3, other coreFormula: PM_INST_FROM_L31_MOD * 100 / PM_L1_ICACHE_MISSINST_FROM_L31_SHR(%)% of ICache reloads from Private L3, other coreFormula: PM_INST_FROM_L31_SHR * 100 / PM_L1_ICACHE_MISSINST_FROM_L3(%)% of ICache reloads from L3Formula: PM_INST_FROM_L3 * 100 / PM_L1_ICACHE_MISSINST_FROM_RL2L3_SHR(%) % of ICache reloads from Remote L2 or L3 (Shared)Formula: PM_INST_FROM_RL2L3_SHR * 100 / PM_L1_ICACHE_MISSINST_FROM_RL2L3_MOD(%) % of ICache reloads from Remote L2 or L3 (Modified)Formula: PM_INST_FROM_RL2L3_MOD * 100 / PM_L1_ICACHE_MISSINST_FROM_DL2L3_MOD(%) % of ICache reloads from Distant L2 or L3 (Modified)Formula: PM_INST_FROM_DL2L3_MOD * 100 / PM_L1_ICACHE_MISSINST_FROM_DL2L3_SHR(%) % of ICache reloads from Distant L2 or L3 (Shared)Formula: PM_INST_FROM_DL2L3_SHR * 100 / PM_L1_ICACHE_MISSINST_FROM_LMEM(%)% of ICache reloads from Local MemoryFormula: PM_INST_FROM_LMEM * 100 / PM_L1_ICACHE_MISSCopyright ©2011 IBM Corporation Page 41 of 52
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Commonly Used Metrics for Performance Analysis - Power.org

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