Commonly Used Metrics for Performance Analysis - Power.org

Metrics for Performance Analysis8 L1 Instruction Cache MissesThis chapter lists and describes the events, metrics and groups needed for analyzing L1 instruction cachemisses.8.1Descriptions of EventsThere are 5 events, distributed across 2 event groups, needed for these POWER7 L1 I-cache miss metrics.These include 1 architected event counting non-idle completed instructions.This section provides more details on each event and how it is triggered.PM_INST_FROM_L2MISSInstruction fetched missed L2The processor's Instruction Cache was reloaded but not from the local L2 due to a demand load.PM_INST_FROM_L3MISSInstruction fetched missed L3The processor's Instruction Cache was reloaded but not from the local L3 due to a demand load.PM_INST_FROM_PREFInstruction fetched from prefetchThe processor's Instruction Cache was reloaded with data because on an instruction prefetch.PM_L1_ICACHE_MISSDemand iCache MissAn instruction fetch missed the L1 Instruction cachePM_RUN_INST_CMPLRun InstructionsNumber of PowerPC instructions completed, gated by the run latch.8.2 MetricsInstruction cache misses are characterized with the following metrics:L1_Inst_Miss_Rate(%)Instruction Cache Miss Rate (Per run Instruction)(%)Formula: PM_L1_ICACHE_MISS * 100 / PM_RUN_INST_CMPLL2_Inst_Miss_Rate(%)L2 Instruction Miss Rate (per instruction)(%)Formula: (PM_INST_FROM_L2MISS - PM_INST_FROM_PREF) * 100 / PM_RUN_INST_CMPLL3_Inst_Miss_Rate(%)L3 Instruction Miss Rate (per instruction)(%)Formula: (PM_INST_FROM_L3MISS - PM_INST_FROM_PREF) * 100 / PM_RUN_INST_CMPLCopyright ©2011 IBM Corporation Page 26 of 52