AD7008 CMOS DDS Modulator

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AD7008CIRCUIT DESCRIPTIONThe AD7008 provides an exciting new level of integration forthe RF/Communications system designer. The AD7008 combinesthe numerically controlled oscillator (NCO), SINE/CO-SINE look-up tables, frequency, phase and IQ modulators, anda digital-to-analog converter on a single integrated circuit.The internal circuitry of the AD7008 consists of four main sections.These are:Numerically Controlled Oscillator (NCO) + Phase ModulatorSINE and COSINE Look-Up TablesIn Phase and Quadrature ModulatorsDigital-to-Analog ConverterThe AD7008 is a fully integrated Direct Digital Synthesis(DDS) chip. The chip requires one reference clock, two lowprecisionresistors and six decoupling capacitors to providedigitally created sine waves up to 25 MHz. In addition to thegeneration of this RF signal, the chip is fully capable of a broadrange of simple and complex modulation schemes. Thesemodulation schemes are fully implemented in the digital domainallowing accurate and simple realization of complex modulationalgorithms using DSP techniques.THEORY OF OPERATIONSine waves are typically thought of in terms of their amplitudeform: a(t) = sin (ωt) or a(t) = cos (ωt). However, these are nonlinearand not easy to generate except through piece wise construction.On the other hand, the angular information is linearin nature. That is, the phase angle rotates though a fixed anglefor each unit of time. The angular rate depends on the frequencyof the signal by the traditional rate of: ω = 2 πf.+10–12π0MAGNITUDEPHASEFigure 9.Knowing that the phase of a sine wave is linear and given a referenceinterval (clock period), the phase rotation for that periodcan be determined.Solving for w:∆Phase =ωdtω= ∆Phasedt= 2 πfSolving for f and substituting the reference clock frequency for⎛the reference period: ⎜⎝1f CLOCK⎞= dt⎟:⎠The AD7008 builds the output based on this simple equation.A simple DDS chip will implement this equation with 3 majorsubcircuits. The AD7008 has an extra section for I and Qmodulation.Numerically Controlled Oscillator + Phase ModulatorThis consists of two frequency select registers, a phase accumulatorand a phase offset register. The main component of theNCO is a 32-bit phase accumulator which assembles the phasecomponent of the output signal. Continuous time signals have aphase range 0 to 2 π. Outside this range of numbers, the sinusoidalfunctions repeat themselves in a periodic manner. Thedigital implementation is no different. The accumulator simplyscales the range of phase numbers into a multibit digital word.The phase accumulator in the AD7008 is implemented with 32bits. Therefore in the AD7008, 2 π = 2 32 . Likewise, the ∆Phaseterm is scaled into this range of numbers 0 ≤ ∆Phase ≤ 2 32 – 1.Making these substitutions into the equation above:f = ∆Phase × f CLOCK2 32 where 0 ≤∆Phase < 2 32With a clock signal of 50 MHz and a phase word of 051EB852hex:f =51EB852 × 50 MHz2 32 = 1.000000000931 MHzThe input to the phase accumulator (i.e., the phase step) can beselected either from the FREQ0 Register or FREQ1 Register,and this is controlled by the FSELECT pin. The phase accumulatorin the AD7008 inherently generates a continuous 32-bit phase signal, thus avoiding any output discontinuity whenswitching between frequencies. This facilitates complex frequencymodulation schemes, such as GMSK.Following the NCO, a phase offset can be added to performphase modulation using the 12-bit PHASE Register. The contentsof this register are added to the most significant bits of theNCO.Sine and Cosine Look-Up TablesTo make the output useful, the signal must be converted fromphase information into a sinusoidal value. Since phase informationmaps directly into amplitude, a ROM look up table convertsthe phase information into amplitude. To do this thedigital phase information is used to address a Sine/Cosine ROMLUT. Only the most significant 12 bits are used for this purpose.The remaining 20 bits provide frequency resolution andminimize the effects of quantization of the phase to amplitudeconversion.In Phase and Quadrature ModulatorsTwo 10-bit amplitude multipliers are provided allowing the easyimplementation of either Quadrature Amplitude Modulation(QAM) or Amplitude Modulation (AM). The 20-bit IQMODRegister is used to control the amplitude of the I (cos) and Q(sin) signals. IQMOD [9:0] controls the I amplitude andIQMOD [19:10] controls the Q amplitude.The user should ensure that when summing the I and Q signalsthe sum should not exceed the value that a 10-bit accumulatorcan hold. The AD7008 does not clip the digital output; theoutput will roll over instead of clip.f = ∆Phase × f CLOCK2 π–8–REV. B
AD7008When amplitude modulation is not required, the IQ multiplierscan be bypassed (CR = 2). The sine output is directly sent tothe 10-bit DAC.Digital-to-Analog ConverterThe AD7008 includes a high impedance current source 10-bitDAC, capable of driving a wide range of loads at differentspeeds. Full-scale output current can be adjusted, for optimumpower and external load requirements, through the use of asingle external resistor (R SET ).The DAC can be configured for single or differential-endedoperation. IOUT can be tied directly to AGND for single-endedoperation or through a load resistor to develop an output voltage.The load resistor can be any value required as long as thefull-scale voltage developed across it does not exceed 1 volt.Since full-scale current is controlled by R SET , adjustments toR SET can balance changes made to the load resistor.DSP and MPU InterfacingThe AD7008 contains a 32-bit parallel assembly register and a32-bit serial assembly register. Each of the modulation registerscan be loaded from either assembly register under control of theLOAD pin and the Transfer-Control (TC) pins (See Table II).The Command register can be loaded only from the parallel assemblyregister. In practical use, both serial and parallel interfacescan be used simultaneously if the application requires.TC3–TC0 should be stable before the LOAD signal rises andshould not change until after LOAD falls (Figure 2).The DSP/MPU asserts both WR and CS to load the parallel assemblyregister (Figure 3). At the end of each write, the parallelassembly register is shifted left by 8 or 16 bits (Depending onCR0), and the new data is loaded into the low bits. Hence, two16-bit writes or four 8-bit writes are used to load the parallel assemblyregister. When loading parallel data, it is only necessaryto write as much data as will be used by that register. For instance,the Command Register requires only one write to theparallel assembly register.Serial data is input to the chip on the rising edge of SCLK, mostsignificant bit first (Figure 4). The data in the assembly registerscan be transferred to the modulation registers by means ofthe transfer control pins.Maximum Updating of the AD7008Updating the AD7008 need not take place in a synchronousfashion. However, in asynchronous systems, most of the externalclock pulses (LOAD and SCLK) must be high for greaterthan one system clock period. This insures that at least oneCLOCK rising edge will occur successfully completing the latchfunction (Figure 1).However, if the AD7008 is run in a synchronous mode with thecontrolling DSP or microcontroller, the AD7008 may be loadedvery rapidly. Optimal speed is attained when operated in the16-bit load mode; the following discussion will assume thatmode is used. Each of the modulation registers require two 16bit loads. This data is latched into the parallel assembly registeron the falling edge of the WR command. This strobe is notqualified by the CLOCK pulse but must be held low for a minimumof 20 ns and only need be high for 10 ns. The two 16-bitwords may be loaded in succession. While the second 16-bitword is being latched into the parallel assembly register, theTransfer and Control word may be presented to the TC3–TC0pins. If the designation register is always the same, an externalregister can be used to store the information on the inputs ofTC3–TC0. At some time after the second falling edge of WR,the LOAD signal may go high. As long as the load signal is high5 ns (see setup time) before the rising edge of the CLOCK signal,data will be transferred to the destination register.The limiting factor of this technique is the WR period which is30 ns. Thus the CLOCK may run up to 33 MSPS using thistechnique and the effective update rate would be one half or16.5 MHz. See timing Figure 10 for timing details.DATAWRCLOCKTCLOADHI WORDLOW WORDFigure 10. Accelerated Data Load SequenceAPPLICATIONSSerial ConfigurationData is written to the AD7008 in serial mode using the two signallines SDATA and SCLK. Data is accumulated in the serialassembly register with the most significant bit loaded first. Thedata bits are loaded on the rising edge of the serial clock. Oncedata is loaded in the serial assembly register, it must be transferredto the appropriate register on chip. This is accomplishedby setting the TC bits according to Tables II and III. If youwant to load the serial assembly register into FREQ1 register,the TC bits should be 1101. When the LOAD pin is raised,data is transferred directly to the FREQ1 register. When operatingin serial mode, some functions must still operate in parallelmode such as loading the TC bits and updating the Commandregister which is accessed only through the parallel assemblyregister. See Figure 11 for a typical serial mode configuration.+5VU21450MHzV CC8OUTV EE7K1115WRLOADSCLKSDATARESETCMD0CMD1CMD2CMD3TC0TC1TC2TC319202122232425268910111213141516273233343536414231303837D0D1D2D3D4D5D6D7D8D9D10D11D12D13D14D15WRU3AD7008CSTC0TC1TC2TC3LOADSCLKSDATAFSELECTCLKRESETSLEEPC16V REF+5V0.1µF C25+5VCOMP0.1µF2 R4IOUT149.9R3IOUT49.9FSADJUSTV AAV DDV DDV DDAGNDDGNDDGNDDGNDDGNDTEST4317283944718294340R5390+5V+5V+5V+5VFigure 11. General Purpose Serial InterfaceREV. B –9–
Page 1 and 2: aFEATURESSingle +5 V Supply32-Bit P
Page 3 and 4: AD7008TIMING CHARACTERISTICS (V AA
Page 5 and 6: AD7008MnemonicFunctionPIN DESCRIPTI
Page 7: AD7008Table I. Latency TableLatency
Page 13 and 14: Typical Performance Characteristics
Page 15 and 16: AD7008AD7008/PCB DDS EVALUATION BOA

AD7008 CMOS DDS Modulator

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