dsPIC33FJ12MC201/202 Data Sheet - Microchip

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dsPIC33FJ12MC201/202FIGURE 1-1:PSV and TableData AccessControl BlockdsPIC33FJ12MC201/202 BLOCK DIAGRAMY Data BusInterruptControllerX Data BusPORTA8161616162323Address Latch23PCU PCH PCLProgram CounterStack LoopControl ControlLogic LogicData LatchX RAMAddressLatch16Data LatchY RAMAddressLatch16Address Generator Units16PORTBRemappablePinsProgram MemoryEA MUXData Latch24ROM Latch16 16InstructionDecode andControlInstruction RegLiteral Data16Control Signalsto Various BlocksDSP EngineOSC2/CLKOOSC1/CLKITimingGenerationFRC/LPRCOscillatorsPrecisionBand GapReferenceVoltageRegulatorPower-upTimerOscillatorStart-up TimerPower-onResetWatchdogTimerBrown-outResetDivide Support16 x 16W Register Array16-bit ALU1616VCAPVDD, VSSMCLRTimers1-3UART1ADC1OC/PWM1-2PWM2 ChSPI1IC1,2,7,8CNxI2C1QEIPWM6 ChNote:Not all pins or features are implemented on all device pinout configurations. See “Pin Diagrams” for the specific pins and featurespresent on each device.DS70265E-page 10© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202TABLE 1-1:Pin NamePinTypePINOUT I/O DESCRIPTIONSBufferTypePPSAN0-AN5 I Analog No Analog input channels.CLKICLKOOSC1OSC2SOSCISOSCOCN0-CN7CN11-CN16CN21-CN24CN27CN29-CN30IC1-IC2IC7-IC8OCFAOC1-OC2INT0INT1INT2IOII/OIOST/CMOS—ST/CMOS—ST/CMOS—NoNoNoNoNoNoI ST NoNoNoNoNoIIIOIIISTSTST—STSTSTYesYesYesYesNoYesYesDescriptionExternal clock source input. Always associated with OSC1 pin function.Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillatormode. Optionally functions as CLKO in RC and EC modes. Always associatedwith OSC2 pin function.Oscillator crystal input. ST buffer when configured in RC mode; CMOSotherwise.Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillatormode. Optionally functions as CLKO in RC and EC modes.32.768 kHz low-power oscillator crystal input; CMOS otherwise.32.768 kHz low-power oscillator crystal output.Change notification inputs.Can be software programmed for internal weak pull-ups on all inputs.Capture inputs 1/2.Capture inputs 7/8.Compare Fault A input (for Compare Channels 1 and 2).Compare outputs 1 through 2.External interrupt 0.External interrupt 1.External interrupt 2.RA0-RA4 I/O ST No PORTA is a bidirectional I/O port.RB0-RB15 I/O ST No PORTB is a bidirectional I/O port.T1CKT2CKT3CKU1CTSU1RTSU1RXU1TXSCK1SDI1SDO1SS1SCL1SDA1ASCL1ASDA1TMSTCKTDITDOIIIIOIOI/OIOI/OI/OI/OI/OI/OIIIOSTSTSTST—ST—STST—STSTSTSTSTSTSTST—NoYesYesYesYesYesYesYesYesYesYesNoNoNoNoNoNoNoNoTimer1 external clock input.Timer2 external clock input.Timer3 external clock input.UART1 clear to send.UART1 ready to send.UART1 receive.UART1 transmit.Synchronous serial clock input/output for SPI1.SPI1 data in.SPI1 data out.SPI1 slave synchronization or frame pulse I/O.Synchronous serial clock input/output for I2C1.Synchronous serial data input/output for I2C1.Alternate synchronous serial clock input/output for I2C1.Alternate synchronous serial data input/output for I2C1.JTAG Test mode select pin.JTAG test clock input pin.JTAG test data input pin.JTAG test data output pin.Legend: CMOS = CMOS compatible input or output Analog = Analog input P = PowerST = Schmitt Trigger input with CMOS levels O = Output I = InputPPS = Peripheral Pin Select© 2007-2011 Microchip Technology Inc. DS70265E-page 11
Page 1 and 2: dsPIC33FJ12MC201/202Data SheetHigh-
Page 3 and 4: dsPIC33FJ12MC201/202High-Performanc
Page 5 and 6: dsPIC33FJ12MC201/202dsPIC33FJ12MC20
Page 7 and 8: dsPIC33FJ12MC201/202Pin Diagrams (C
Page 9: dsPIC33FJ12MC201/2021.0 DEVICE OVER
Page 13 and 14: dsPIC33FJ12MC201/2021.1 Referenced
Page 15 and 16: dsPIC33FJ12MC201/2022.0 GUIDELINES
Page 17 and 18: dsPIC33FJ12MC201/2022.5 ICSP PinsTh
Page 19 and 20: dsPIC33FJ12MC201/2023.0 CPUNote 1:
Page 21 and 22: dsPIC33FJ12MC201/202FIGURE 3-2:dsPI
Page 23 and 24: dsPIC33FJ12MC201/202REGISTER 3-1:SR
Page 25 and 26: dsPIC33FJ12MC201/2023.5 Arithmetic
Page 27 and 28: dsPIC33FJ12MC201/2023.6.1 MULTIPLIE
Page 29 and 30: dsPIC33FJ12MC201/2023.6.3.1 Round L
Page 31 and 32: dsPIC33FJ12MC201/2024.0 MEMORY ORGA
Page 33 and 34: dsPIC33FJ12MC201/2024.2 Data Addres
Page 35 and 36: dsPIC33FJ12MC201/2024.2.5 X AND Y D
Page 37 and 38: © 2007-2011 Microchip Technology I
Page 49 and 50: dsPIC33FJ12MC201/202TABLE 4-26:FUND
Page 51 and 52: dsPIC33FJ12MC201/2024.4.3 MODULO AD
Page 53 and 54: dsPIC33FJ12MC201/2024.6 Interfacing
Page 55 and 56: dsPIC33FJ12MC201/2024.6.2 DATA ACCE
Page 57 and 58: dsPIC33FJ12MC201/2025.0 FLASH PROGR
Page 59 and 60: dsPIC33FJ12MC201/202REGISTER 5-1:NV
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dsPIC33FJ12MC201/2025.4.1 PROGRAMMI
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dsPIC33FJ12MC201/2026.0 RESETSNote
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dsPIC33FJ12MC201/202REGISTER 6-1:RC
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dsPIC33FJ12MC201/202FIGURE 6-2:SYST
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dsPIC33FJ12MC201/2026.4 External Re
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dsPIC33FJ12MC201/2027.0 INTERRUPT C
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dsPIC33FJ12MC201/202TABLE 7-1:Vecto
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dsPIC33FJ12MC201/2027.3 Interrupt C
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dsPIC33FJ12MC201/202REGISTER 7-3: I
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dsPIC33FJ12MC201/202REGISTER 7-5:IF
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dsPIC33FJ12MC201/202REGISTER 7-10:
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dsPIC33FJ12MC201/2027.4 Interrupt S
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dsPIC33FJ12MC201/2028.0 OSCILLATORC
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dsPIC33FJ12MC201/2028.1.3 PLL CONFI
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dsPIC33FJ12MC201/202REGISTER 8-1: O
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dsPIC33FJ12MC201/202REGISTER 8-2: C
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dsPIC33FJ12MC201/202REGISTER 8-4: O
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dsPIC33FJ12MC201/2029.0 POWER-SAVIN
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dsPIC33FJ12MC201/202REGISTER 9-1: P
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dsPIC33FJ12MC201/202REGISTER 9-3: P
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dsPIC33FJ12MC201/20210.0 I/O PORTSN
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dsPIC33FJ12MC201/20210.4 Peripheral
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dsPIC33FJ12MC201/202TABLE 10-2:OUTP
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dsPIC33FJ12MC201/20211.0 TIMER1Note
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dsPIC33FJ12MC201/20212.0 TIMER2/3 F
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dsPIC33FJ12MC201/202FIGURE 12-2:TIM
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dsPIC33FJ12MC201/202REGISTER 12-2:T
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dsPIC33FJ12MC201/20213.0 INPUT CAPT
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dsPIC33FJ12MC201/20214.0 OUTPUT COM
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dsPIC33FJ12MC201/202FIGURE 14-2:OUT
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dsPIC33FJ12MC201/20215.0 MOTOR CONT
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dsPIC33FJ12MC201/202FIGURE 15-2:2-C
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dsPIC33FJ12MC201/202REGISTER 15-2:P
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dsPIC33FJ12MC201/20216.0 QUADRATURE
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dsPIC33FJ12MC201/202REGISTER 16-1:Q
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dsPIC33FJ12MC201/20217.0 SERIAL PER
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dsPIC33FJ12MC201/20218.0 INTER-INTE
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dsPIC33FJ12MC201/202REGISTER 18-1:I
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dsPIC33FJ12MC201/20219.0 UNIVERSAL
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dsPIC33FJ12MC201/202REGISTER 19-1:U
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dsPIC33FJ12MC201/202REGISTER 19-2:U
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dsPIC33FJ12MC201/20220.0 10-BIT/12-
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dsPIC33FJ12MC201/202FIGURE 20-2:ADC
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dsPIC33FJ12MC201/202REGISTER 20-4:A
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dsPIC33FJ12MC201/202REGISTER 20-5:A
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dsPIC33FJ12MC201/20221.0 SPECIAL FE
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dsPIC33FJ12MC201/202TABLE 21-2:Bit
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dsPIC33FJ12MC201/20221.4 Watchdog T
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dsPIC33FJ12MC201/20222.0 INSTRUCTIO
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dsPIC33FJ12MC201/202TABLE 22-1:Fiel
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dsPIC33FJ12MC201/202TABLE 22-2:Base
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dsPIC33FJ12MC201/202TABLE 22-2:Base
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dsPIC33FJ12MC201/20223.0 DEVELOPMEN
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dsPIC33FJ12MC201/20223.7 MPLAB SIM
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dsPIC33FJ12MC201/20224.0 ELECTRICAL
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dsPIC33FJ12MC201/202TABLE 24-4: DC
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dsPIC33FJ12MC201/202TABLE 24-9:DC C
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dsPIC33FJ12MC201/202TABLE 24-9:DC C
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dsPIC33FJ12MC201/202FIGURE 24-2:EXT
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dsPIC33FJ12MC201/202FIGURE 24-3:CLK
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dsPIC33FJ12MC201/202TABLE 24-21:AC
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dsPIC33FJ12MC201/202TABLE 24-26: IN
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dsPIC33FJ12MC201/202TABLE 24-29: MO
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dsPIC33FJ12MC201/202TABLE 24-33: SP
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dsPIC33FJ12MC201/202FIGURE 24-17:SP
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dsPIC33FJ12MC201/202TABLE 24-40: I2
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dsPIC33FJ12MC201/202TABLE 24-41:I2C
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dsPIC33FJ12MC201/202TABLE 24-43: AD
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dsPIC33FJ12MC201/202FIGURE 24-26:AD
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dsPIC33FJ12MC201/2023.0 TAD — Aut
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dsPIC33FJ12MC201/20225.0 PACKAGING
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dsPIC33FJ12MC201/20225.2 Package De
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dsPIC33FJ12MC201/202Note:For the mo
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dsPIC33FJ12MC201/20228-Lead Skinny
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dsPIC33FJ12MC201/20228-Lead Plastic
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dsPIC33FJ12MC201/202APPENDIX A:Revi
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dsPIC33FJ12MC201/202TABLE 25-1:Sect
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dsPIC33FJ12MC201/202TABLE 25-3:MAJO
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dsPIC33FJ12MC201/202INDEXAAC Charac
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dsPIC33FJ12MC201/202IPC3 (Interrupt
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dsPIC33FJ12MC201/202THE MICROCHIP W
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dsPIC33FJ12MC201/202PRODUCT IDENTIF
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