dsPIC33FJ12MC201/202 Data Sheet - Microchip

dsPIC33FJ12MC201/202TABLE 1-1:Pin NamePinTypePINOUT I/O DESCRIPTIONS (CONTINUED)BufferTypePPSDescriptionINDXQEAQEBUPDNIIIOSTSTSTCMOSYesYesYesYesQuadrature Encoder Index Pulse input.Quadrature Encoder Phase A input in QEI mode.Auxiliary Timer External Clock/Gate input in Timer mode.Quadrature Encoder Phase A input in QEI mode.Auxiliary Timer External Clock/Gate input in Timer mode.Position Up/Down Counter Direction State.FLTA1PWM1L1PWM1H1PWM1L2PWM1H2PWM1L3PWM1H3IOOOOOOST——————YesNoNoNoNoNoNoPWM1 Fault A input.PWM1 Low output 1PWM1 High output 1PWM1 Low output 2PWM1 High output 2PWM1 Low output 3PWM1 High output 3FLTA2 I ST Yes PWM2 Fault A input.PWM2L1 O — No PWM2 Low output 1PWM2H1 O — No PWM2 High output 1PGED1PGEC1PGED2PGEC2PGED3PGEC3I/OII/OII/OISTSTSTSTSTSTNoNoNoNoNoNoData I/O pin for programming/debugging communication channel 1.Clock input pin for programming/debugging communication channel 1.Data I/O pin for programming/debugging communication channel 2.Clock input pin for programming/debugging communication channel 2.Data I/O pin for programming/debugging communication channel 3.Clock input pin for programming/debugging communication channel 3.MCLR I/P ST No Master Clear (Reset) input. This pin is an active-low Reset to the device.AVDD P P No Positive supply for analog modules. This pin must be connected at all times.AVSS P P No Ground reference for analog modules.VDD P — No Positive supply for peripheral logic and I/O pins.VCAP P — No CPU logic filter capacitor connection.VSS P — No Ground reference for logic and I/O pins.VREF+ I Analog No Analog voltage reference (high) input.VREF- I Analog No Analog voltage reference (low) input.Legend: CMOS = CMOS compatible input or output Analog = Analog input P = PowerST = Schmitt Trigger input with CMOS levels O = Output I = InputPPS = Peripheral Pin SelectDS70265E-page 12© 2007-2011 Microchip Technology Inc.