dsPIC33FJ12MC201/202 Data Sheet - Microchip

dsPIC33FJ12MC201/2024.2.6 SOFTWARE STACKIn addition to its use as a working register, the W15register in the dsPIC33FJ12MC201/202 devices is alsoused as a software Stack Pointer. The Stack Pointeralways points to the first available free word and growsfrom lower to higher addresses. It pre-decrements forstack pops and post-increments for stack pushes, asshown in Figure 4-4. For a PC push during any CALLinstruction, the MSb of the PC is zero-extended beforethe push, ensuring that the MSb is always clear.Note:The Stack Pointer Limit register (SPLIM) associatedwith the Stack Pointer sets an upper address boundaryfor the stack. SPLIM is uninitialized at Reset. As is thecase for the Stack Pointer, SPLIM is forced to ‘0’because all stack operations must be word aligned.Whenever an EA is generated using W15 as a sourceor destination pointer, the resulting address iscompared with the value in SPLIM. If the contents ofthe Stack Pointer (W15) and the SPLIM register areequal and a push operation is performed, a stack errortrap will not occur. However, the stack error trap willoccur on a subsequent push operation. For example, tocause a stack error trap when the stack grows beyondaddress 0x0C00 in RAM, initialize the SPLIM with thevalue 0x0BFE.Similarly, a Stack Pointer underflow (stack error) trap isgenerated when the Stack Pointer address is found tobe less than 0x0800. This prevents the stack frominterfering with the SFR space.A write to the SPLIM register should not be immediatelyfollowed by an indirect read operation using W15.FIGURE 4-4:0x0000Stack Grows TowardHigher AddressA PC push during exception processingconcatenates the SRL register to the MSbof the PC prior to the push.15PC000000000 PCCALL STACK FRAME0W15 (before CALL)W15 (after CALL)POP : [--W15]PUSH : [W15++]4.2.7 DATA RAM PROTECTION FEATUREThe dsPIC33F product family supports Data RAMprotection features that enable segments of RAM to beprotected when used in conjunction with Boot andSecure Code Segment Security. BSRAM (Secure RAMsegment for BS) is accessible only from the BootSegment Flash code, when enabled. SSRAM (SecureRAM segment for RAM) is accessible only from theSecure Segment Flash code, when enabled. SeeTable 4-1 for an overview of the BSRAM and SSRAMSFRs.4.3 Instruction Addressing ModesThe addressing modes shown in Table 4-26 form thebasis of the addressing modes that are optimized tosupport the specific features of individual instructions.The addressing modes provided in the MAC class ofinstructions differ from those provided in otherinstruction types.4.3.1 FILE REGISTER INSTRUCTIONSMost file register instructions use a 13-bit address field(f) to directly address data present in the first 8192bytes of data memory (near data space). Most fileregister instructions employ a working register, W0,which is denoted as WREG in these instructions. Thedestination is typically either the same file register orWREG (with the exception of the MUL instruction),which writes the result to a register or register pair. TheMOV instruction allows additional flexibility and canaccess the entire data space.4.3.2 MCU INSTRUCTIONSThe three-operand MCU instructions are of the form:Operand 3 = Operand 1 Operand 2where Operand 1 is always a working register (that is,the addressing mode can only be register direct), whichis referred to as Wb. Operand 2 can be a W register,fetched from data memory, or a 5-bit literal. The resultlocation can be either a W register or a data memorylocation. The following addressing modes aresupported by MCU instructions:• Register Direct• Register Indirect• Register Indirect Post-Modified• Register Indirect Pre-Modified• 5-bit or 10-bit LiteralNote: Not all instructions support all theaddressing modes given above.Individual instructions can supportdifferent subsets of these addressingmodes.DS70265E-page 48© 2007-2011 Microchip Technology Inc.