dsPIC33FJ12MC201/202 Data Sheet - Microchip

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dsPIC33FJ12MC201/202FIGURE 4-3:DATA MEMORY MAP FOR dsPIC33FJ12MC201/202 DEVICES WITH 1 KB RAMMSBAddress16 bitsLSBAddress2 KbyteSFR Space1 KbyteSRAM Space0x00010x07FF0x08010x09FF0x0A010x0BFF0x0C01MSbLSbSFR SpaceX Data RAM (X)Y Data RAM (Y)0x00000x07FE0x08000x09FE0x0A000x0BFE0x0C008 KbyteNear DataSpace0x1FFF0x20010x1FFE0x20000x80010x8000OptionallyMappedinto ProgramMemoryX DataUnimplemented (X)0xFFFF0xFFFEDS70265E-page 34© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/2024.2.5 X AND Y DATA SPACESThe core has two data spaces, X and Y. These dataspaces can be considered either separate (for someDSP instructions), or as one unified linear addressrange (for MCU instructions). The data spaces areaccessed using two Address Generation Units (AGUs)and separate data paths. This feature allows certaininstructions to concurrently fetch two words from RAM,thereby enabling efficient execution of DSP algorithmssuch as Finite Impulse Response (FIR) filtering andfast Fourier transform (FFT).The X data space is used by all instructions andsupports all addressing modes. X data space hasseparate read and write data buses. The X read databus is the read data path for all instructions that viewdata space as combined X and Y address space. It isalso the X data prefetch path for the dual operand DSPinstructions (MAC class).The Y data space is used in concert with the X dataspace by the MAC class of instructions (CLR, ED,EDAC, MAC, MOVSAC, MPY, MPY.N, and MSC) to providetwo concurrent data read paths.Both the X and Y data spaces support ModuloAddressing mode for all instructions, subject toaddressing mode restrictions. Bit-Reversed Addressingmode is only supported for writes to X data space.All data memory writes, including in DSP instructions,view data space as combined X and Y address space.The boundary between the X and Y data spaces isdevice-dependent and is not user-programmable.All effective addresses are 16 bits wide and point tobytes within the data space. Therefore, the data spaceaddress range is 64 Kbytes, or 32K words, although theimplemented memory locations vary by device.© 2007-2011 Microchip Technology Inc. DS70265E-page 35
Page 1 and 2: dsPIC33FJ12MC201/202Data SheetHigh-
Page 3 and 4: dsPIC33FJ12MC201/202High-Performanc
Page 5 and 6: dsPIC33FJ12MC201/202dsPIC33FJ12MC20
Page 7 and 8: dsPIC33FJ12MC201/202Pin Diagrams (C
Page 9 and 10: dsPIC33FJ12MC201/2021.0 DEVICE OVER
Page 11 and 12: dsPIC33FJ12MC201/202TABLE 1-1:Pin N
Page 13 and 14: dsPIC33FJ12MC201/2021.1 Referenced
Page 15 and 16: dsPIC33FJ12MC201/2022.0 GUIDELINES
Page 17 and 18: dsPIC33FJ12MC201/2022.5 ICSP PinsTh
Page 19 and 20: dsPIC33FJ12MC201/2023.0 CPUNote 1:
Page 21 and 22: dsPIC33FJ12MC201/202FIGURE 3-2:dsPI
Page 23 and 24: dsPIC33FJ12MC201/202REGISTER 3-1:SR
Page 25 and 26: dsPIC33FJ12MC201/2023.5 Arithmetic
Page 27 and 28: dsPIC33FJ12MC201/2023.6.1 MULTIPLIE
Page 29 and 30: dsPIC33FJ12MC201/2023.6.3.1 Round L
Page 31 and 32: dsPIC33FJ12MC201/2024.0 MEMORY ORGA
Page 33: dsPIC33FJ12MC201/2024.2 Data Addres
Page 37 and 38: © 2007-2011 Microchip Technology I
Page 49 and 50: dsPIC33FJ12MC201/202TABLE 4-26:FUND
Page 51 and 52: dsPIC33FJ12MC201/2024.4.3 MODULO AD
Page 53 and 54: dsPIC33FJ12MC201/2024.6 Interfacing
Page 55 and 56: dsPIC33FJ12MC201/2024.6.2 DATA ACCE
Page 57 and 58: dsPIC33FJ12MC201/2025.0 FLASH PROGR
Page 59 and 60: dsPIC33FJ12MC201/202REGISTER 5-1:NV
Page 61 and 62: dsPIC33FJ12MC201/2025.4.1 PROGRAMMI
Page 63 and 64: dsPIC33FJ12MC201/2026.0 RESETSNote
Page 65 and 66: dsPIC33FJ12MC201/202REGISTER 6-1:RC
Page 67 and 68: dsPIC33FJ12MC201/202FIGURE 6-2:SYST
Page 69 and 70: dsPIC33FJ12MC201/2026.4 External Re
Page 71 and 72: dsPIC33FJ12MC201/2027.0 INTERRUPT C
Page 73 and 74: dsPIC33FJ12MC201/202TABLE 7-1:Vecto
Page 75 and 76: dsPIC33FJ12MC201/2027.3 Interrupt C
Page 77 and 78: dsPIC33FJ12MC201/202REGISTER 7-3: I
Page 81 and 82: dsPIC33FJ12MC201/202REGISTER 7-5:IF
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dsPIC33FJ12MC201/202REGISTER 7-9: I
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dsPIC33FJ12MC201/202REGISTER 7-10:
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dsPIC33FJ12MC201/2027.4 Interrupt S
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dsPIC33FJ12MC201/2028.0 OSCILLATORC
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dsPIC33FJ12MC201/2028.1.3 PLL CONFI
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dsPIC33FJ12MC201/202REGISTER 8-1: O
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dsPIC33FJ12MC201/202REGISTER 8-2: C
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dsPIC33FJ12MC201/202REGISTER 8-4: O
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dsPIC33FJ12MC201/2029.0 POWER-SAVIN
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dsPIC33FJ12MC201/202REGISTER 9-1: P
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dsPIC33FJ12MC201/202REGISTER 9-3: P
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dsPIC33FJ12MC201/20210.0 I/O PORTSN
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dsPIC33FJ12MC201/20210.4 Peripheral
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dsPIC33FJ12MC201/202TABLE 10-2:OUTP
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dsPIC33FJ12MC201/20211.0 TIMER1Note
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dsPIC33FJ12MC201/20212.0 TIMER2/3 F
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dsPIC33FJ12MC201/202FIGURE 12-2:TIM
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dsPIC33FJ12MC201/202REGISTER 12-2:T
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dsPIC33FJ12MC201/20213.0 INPUT CAPT
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dsPIC33FJ12MC201/20214.0 OUTPUT COM
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dsPIC33FJ12MC201/202FIGURE 14-2:OUT
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dsPIC33FJ12MC201/20215.0 MOTOR CONT
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dsPIC33FJ12MC201/202FIGURE 15-2:2-C
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dsPIC33FJ12MC201/202REGISTER 15-2:P
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dsPIC33FJ12MC201/20216.0 QUADRATURE
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dsPIC33FJ12MC201/202REGISTER 16-1:Q
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dsPIC33FJ12MC201/20217.0 SERIAL PER
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dsPIC33FJ12MC201/20218.0 INTER-INTE
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dsPIC33FJ12MC201/202REGISTER 18-1:I
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dsPIC33FJ12MC201/20219.0 UNIVERSAL
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dsPIC33FJ12MC201/202REGISTER 19-1:U
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dsPIC33FJ12MC201/202REGISTER 19-2:U
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dsPIC33FJ12MC201/20220.0 10-BIT/12-
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dsPIC33FJ12MC201/202FIGURE 20-2:ADC
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dsPIC33FJ12MC201/202REGISTER 20-4:A
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dsPIC33FJ12MC201/202REGISTER 20-5:A
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dsPIC33FJ12MC201/20221.0 SPECIAL FE
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dsPIC33FJ12MC201/202TABLE 21-2:Bit
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dsPIC33FJ12MC201/20221.4 Watchdog T
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dsPIC33FJ12MC201/20222.0 INSTRUCTIO
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dsPIC33FJ12MC201/202TABLE 22-1:Fiel
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dsPIC33FJ12MC201/202TABLE 22-2:Base
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dsPIC33FJ12MC201/202TABLE 22-2:Base
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dsPIC33FJ12MC201/20223.0 DEVELOPMEN
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dsPIC33FJ12MC201/20223.7 MPLAB SIM
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dsPIC33FJ12MC201/20224.0 ELECTRICAL
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dsPIC33FJ12MC201/202TABLE 24-4: DC
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dsPIC33FJ12MC201/202TABLE 24-9:DC C
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dsPIC33FJ12MC201/202TABLE 24-9:DC C
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dsPIC33FJ12MC201/202FIGURE 24-2:EXT
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dsPIC33FJ12MC201/202FIGURE 24-3:CLK
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dsPIC33FJ12MC201/202TABLE 24-21:AC
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dsPIC33FJ12MC201/202TABLE 24-26: IN
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dsPIC33FJ12MC201/202TABLE 24-29: MO
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dsPIC33FJ12MC201/202TABLE 24-33: SP
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dsPIC33FJ12MC201/202FIGURE 24-17:SP
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dsPIC33FJ12MC201/202TABLE 24-40: I2
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dsPIC33FJ12MC201/202TABLE 24-41:I2C
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dsPIC33FJ12MC201/202TABLE 24-43: AD
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dsPIC33FJ12MC201/202FIGURE 24-26:AD
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dsPIC33FJ12MC201/2023.0 TAD — Aut
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dsPIC33FJ12MC201/20225.0 PACKAGING
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dsPIC33FJ12MC201/20225.2 Package De
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dsPIC33FJ12MC201/202Note:For the mo
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dsPIC33FJ12MC201/20228-Lead Skinny
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dsPIC33FJ12MC201/20228-Lead Plastic
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dsPIC33FJ12MC201/202APPENDIX A:Revi
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dsPIC33FJ12MC201/202TABLE 25-1:Sect
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dsPIC33FJ12MC201/202TABLE 25-3:MAJO
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dsPIC33FJ12MC201/202INDEXAAC Charac
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dsPIC33FJ12MC201/202IPC3 (Interrupt
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dsPIC33FJ12MC201/202THE MICROCHIP W
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dsPIC33FJ12MC201/202PRODUCT IDENTIF
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