dsPIC33FJ12MC201/202 Data Sheet - Microchip

dsPIC33FJ12MC201/2024.1.1 PROGRAM MEMORYORGANIZATIONThe program memory space is organized in wordaddressableblocks. Although it is treated as 24 bitswide, it is more appropriate to think of each address ofthe program memory as a lower and upper word, withthe upper byte of the upper word being unimplemented.The lower word always has an even address, while theupper word has an odd address (Figure 4-2).Program memory addresses are always word-alignedon the lower word, and addresses are incremented ordecremented by two during code execution. Thisarrangement provides compatibility with data memoryspace addressing and makes data in the programmemory space accessible.4.1.2 INTERRUPT AND TRAP VECTORSAll dsPIC33FJ12MC201/202 devices reserve theaddresses between 0x00000 and 0x000200 for hardcodedprogram execution vectors. A hardware Resetvector is provided to redirect code execution from thedefault value of the PC on device Reset to the actualstart of code. A GOTO instruction is programmed by theuser application at 0x000000, with the actual addressfor the start of code at 0x000002.dsPIC33FJ12MC201/202 devices also have twointerrupt vector tables, located from 0x000004 to0x0000FF and 0x000100 to 0x0001FF. These vectortables allow each of the device interrupt sources to behandled by separate Interrupt Service Routines (ISRs).A more detailed discussion of the interrupt vectortables is provided in Section 7.1 “Interrupt VectorTable”.FIGURE 4-2:PROGRAM MEMORY ORGANIZATIONmswAddressmost significant word (msw)least significant word (lsw)PC Address(lsw Address)0x0000010x0000030x0000050x000007000000000000000000000000000000002316800x0000000x0000020x0000040x000006Program Memory‘Phantom’ Byte(read as ‘0’)Instruction WidthDS70265E-page 32© 2007-2011 Microchip Technology Inc.