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dsPIC33FJ12MC201/202 Data Sheet - Microchip

dsPIC33FJ12MC201/202 Data Sheet - Microchip

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<strong>dsPIC33FJ12MC201</strong>/<strong>202</strong>REGISTER 3-2:CORCON: CORE CONTROL REGISTERU-0 U-0 U-0 R/W-0 R/W-0 R-0 R-0 R-0— — — US EDT (1) DLbit 15 bit 8R/W-0 R/W-0 R/W-1 R/W-0 R/C-0 R/W-0 R/W-0 R/W-0SATA SATB SATDW ACCSAT IPL3 (2) PSV RND IFbit 7 bit 0Legend:C = Clear only bitR = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set0’ = Bit is cleared ‘x = Bit is unknown U = Unimplemented bit, read as ‘0’bit 15-13 Unimplemented: Read as ‘0’bit 12 US: DSP Multiply Unsigned/Signed Control bit1 = DSP engine multiplies are unsigned0 = DSP engine multiplies are signedbit 11 EDT: Early DO Loop Termination Control bit (1)1 = Terminate executing DO loop at end of current loop iteration0 = No effectbit 10-8 DL: DO Loop Nesting Level Status bits111 = 7 DO loops active•••001 = 1 DO loop active000 = 0 DO loops activebit 7SATA: ACCA Saturation Enable bit1 = Accumulator A saturation enabled0 = Accumulator A saturation disabledbit 6SATB: ACCB Saturation Enable bit1 = Accumulator B saturation enabled0 = Accumulator B saturation disabledbit 5SATDW: <strong>Data</strong> Space Write from DSP Engine Saturation Enable bit1 = <strong>Data</strong> space write saturation enabled0 = <strong>Data</strong> space write saturation disabledbit 4ACCSAT: Accumulator Saturation Mode Select bit1 = 9.31 saturation (super saturation)0 = 1.31 saturation (normal saturation)bit 3 IPL3: CPU Interrupt Priority Level Status bit 3 (2)bit 2bit 1bit 01 = CPU interrupt priority level is greater than 70 = CPU interrupt priority level is 7 or lessPSV: Program Space Visibility in <strong>Data</strong> Space Enable bit1 = Program space visible in data space0 = Program space not visible in data spaceRND: Rounding Mode Select bit1 = Biased (conventional) rounding enabled0 = Unbiased (convergent) rounding enabledIF: Integer or Fractional Multiplier Mode Select bit1 = Integer mode enabled for DSP multiply ops0 = Fractional mode enabled for DSP multiply opsNote 1: This bit will always read as ‘0’.2: The IPL3 bit is concatenated with the IPL bits (SR) to form the CPU interrupt priority level.DS70265E-page 24© 2007-2011 <strong>Microchip</strong> Technology Inc.

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