Design Checklist for PowerQUICC II Pro MPC8309 Processor

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JTAG and Debug COP_TDO COP_TDI NC COP_TCK COP_TMS COP_SRESET COP_HRESET COP_CHKSTP_OUT 1 2 3 5 7 9 11 13 15 Figure 6. COP Connector Physical Pinout Design Checklist for PowerQUICC II Pro MPC8309 Processor, Rev. 1 14 Freescale Semiconductor 4 6 8 10 12 KEY No pin 16 NC COP_TRST COP_VDD_SENSE COP_CHKSTP_IN NC NC GND
From Target Board Sources (if any) 1 2 3 5 7 9 11 13 15 4 6 8 10 12 KEY No pin 16 COP Connector Physical Pinout COP Header PORESET HRESET 13 11 4 6 5 15 14 3 COP_HRESET COP_TRST COP_VDD_SENSE 2 COP_CHKSTP_IN 8 COP_TMS 9 COP_TDO 1 COP_TDI 3 COP_TCK 7 2 10 12 16 NC NC COP_CHKSTP_OUT NC NC 4 B 5 A Figure 7. JTAG Interface Connection Design Checklist for PowerQUICC II Pro MPC8309 Processor, Rev. 1 JTAG and Debug Notes: 1. The COP port and target board must be able to assert PORESET and TRST independently to the processor to control the processor fully as shown here. 2. Populate this with a 10 � resistor for short-circuit/current-limiting protection. 3. The KEY location (pin 14) is not physically present on the COP header. 4. Although pin 12 is defined as a No-Connect, some debug tools may use pin 12 as an additional GND pin for improved signal integrity. 5. This switch is included as a precaution for BSDL testing. The switch must be closed to position A during BSDL testing to avoid accidentally asserting the /TRST line. If BSDL testing is not being performed, this switch must be closed to position B. 10 � 10 k� Freescale Semiconductor 15 10 k� 10 k� 10 k� 10 k� 10 k� 10 k� 10 k� OV DD PORESET 1 HRESET TRST 1 CKSTOP_OUT CKSTOP_IN TMS TDO TDI TCK
Page 1 and 2: Freescale Semiconductor Application
Page 3 and 4: atings only and functional operatio
Page 5 and 6: 2.6 PLL Power Supply Filtering Desi
Page 7 and 8: 4 Clocking Figure 3 shows the inter
Page 9 and 10: Design Checklist for PowerQUICC II
Page 13: Design Checklist for PowerQUICC II
Page 17 and 18: Table 7 summarizes the DDR SDRAM pi
Page 21 and 22: 7.3 PCI Bus Interface Design Checkl
Page 23 and 24: Signal PCI_GNT[0] I/O External arbi
Page 25 and 26: Signal Pin Type USBDR_TXDRXD[3]/ GP
Page 27 and 28: 7.6 DUART Table 13 lists the dual U
Page 29 and 30: 7.9 QUICC Engine Communication Inte
Page 31 and 32: Signal Pin Type FEC2_RXD[3] / GPIO[
Page 33 and 34: 7.9.2 HDLC/TDM Ports The QUICC Engi
Page 35 and 36: Signal Pin Type SD_CD I As needed +
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Design Checklist for PowerQUICC II Pro MPC8309 Processor

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