Design Checklist for PowerQUICC II Pro MPC8309 Processor

Revision History
Signal Pin Type
RXCAN4 I As Needed 1 - 4.7k� to
GND
TXCAN4 O As Needed 1 - 4.7k� to
GND
8 Revision History
Table 20 provides a revision history for this application note.
Rev.
Number
Table 20. Document Revision History
Date Substantive Change(s)
Pin functionality determined by SICR_1[20-21] bit setting
Pin functionality determined by SICR_1[20-21] bit setting
1 05/2012 In Table 4, “Reset Configuration Pin Listing,” replaced HRESET with PORESET in
the termination column for CFG_RESET_SOURCE[n].
In Table 9, “Local Bus Pin ListingFor Signals,” replaced the "if not used" column
value for LGPL4/LGTA_B/LUPWAIT/LFRB_B signal from "Open" to "4.7k� – 10k��
to OVDD".
In Table 11, “ULPI Pin Listing,” deleted the signals QE_TRB_O and QE_TRB_I .
In Table 18, “eSDHC Pin Listing,” modified the description of connections “If used”,
and notes.
0 03/2011 Initial release.
Table 19. FlexCAN Pin Listing (continued)
If Used
Connection
If Not
Used
Design Checklist for PowerQUICC II Pro MPC8309 Processor, Rev. 1
36 Freescale Semiconductor
Notes