Design Checklist for PowerQUICC II Pro MPC8309 Processor

Functional Blocks
7.2.1 Local Bus Address
Figure 8 shows the correct way to make the address for the local bus.
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MPC8309 Local Bus Interface
LCLK
LAD
LALE
LCSn
LAD[0:15]
LALE
LA[16:25]
D
LE
D
Figure 8. Local Bus Address
Figure 9. LALE Timing
LA[0:15]
For every assertion of LCSn, LALE is asserted first. While LALE is asserted, all other control signals are
negated. The duration of LALE can be programmed to 1–4 cycles in LCRR[EADC]. The default is 4
cycles. The timing of LALE negation is important to ensure that the correct address is latched.
Table 8 lists guidelines for connecting to 8-bit, and 16-bit devices. LAD[0] is the most significant address
and data bit, and LAD[15] is the least significant address and data bit. Note that for a 16-bit port
Design Checklist for PowerQUICC II Pro MPC8309 Processor, Rev. 1
LA[0:25]
18 Freescale Semiconductor
Q
Latch
Address Write Data
A Latched Address
TA