Design Checklist for PowerQUICC II Pro MPC8309 Processor

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Functional Blocks Signal Pin Type FEC3_TX_ER / GPIO[59] FEC3_TXD[0]/ GPIO[60] FEC3_TXD[1] / GPIO[61] FEC3_TXD[2] / GPIO[62] FEC3_TXD[3] / GPIO[63] Table 16. FEC Pin Listing (continued) Connection If Used If Not Used I/O As needed Open — I/O As needed Open — I/O As needed Open — I/O As needed Open — I/O As needed Open — Design Checklist for PowerQUICC II Pro MPC8309 Processor, Rev. 1 32 Freescale Semiconductor Notes
7.9.2 HDLC/TDM Ports The QUICC Engine supports two HDLC/TDM ports. Table 17 lists the HDLC/TDM port signals. Table 17. HDLC/TDM Port Signals Signal Pin Type HDLC1_RXCLK/ TDM1_RCK/ GPIO[1] HDLC1_RXD/ TDM1_RD/ GPIO[3] HDLC1_TXCLK/ TDM1_TCK/ GPIO[0] HDLC1_CD/ TDM1_TFS/ GPIO[4] HDLC1_CTS/ TDM1_RFS/ GPIO[5] HDLC2_TXCLK/ TDM2_TCK/ GPIO[16] HDLC2_RXCLK/ TDM2_RCK/ GPIO[17] HDLC2_RXD/ TDM2_RD/ GPIO[19] HDLC2_CD/ TDM2_TFS/ GPIO[20] HDLC2_CTS/ TDM2_RFS/ GPIO[21] Connection If Used If Not Used Design Checklist for PowerQUICC II Pro MPC8309 Processor, Rev. 1 Functional Blocks Freescale Semiconductor 33 Notes I/O As needed Open If unused and left open, configure this pin as output I/O As needed 1 k� to GND — I/O As needed Open If unused and left open, configure this pin as output I/O As needed 2 k–10 k� to OV DD — I/O As needed 2 k–10 k� to OV DD — I/O As needed Open If unused and left open, configure this pin as output I/O As needed Open If unused and left open, configure this pin as output I/O As needed 1 k� to GND — I/O As needed 2 k–10 k� to OV DD — I/O As needed 2 k–10 k� to OV DD —
Page 1 and 2: Freescale Semiconductor Application
Page 3 and 4: atings only and functional operatio
Page 5 and 6: 2.6 PLL Power Supply Filtering Desi
Page 7 and 8: 4 Clocking Figure 3 shows the inter
Page 9 and 10: Design Checklist for PowerQUICC II
Page 15 and 16: From Target Board Sources (if any)
Page 17 and 18: Table 7 summarizes the DDR SDRAM pi
Page 21 and 22: 7.3 PCI Bus Interface Design Checkl
Page 23 and 24: Signal PCI_GNT[0] I/O External arbi
Page 25 and 26: Signal Pin Type USBDR_TXDRXD[3]/ GP
Page 27 and 28: 7.6 DUART Table 13 lists the dual U
Page 29 and 30: 7.9 QUICC Engine Communication Inte
Page 31: Signal Pin Type FEC2_RXD[3] / GPIO[
Page 35 and 36: Signal Pin Type SD_CD I As needed +
Page 37: How to Reach Us: Home Page: www.fre

Design Checklist for PowerQUICC II Pro MPC8309 Processor

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