Design Checklist for PowerQUICC II Pro MPC8309 Processor

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Pin Listing and Connections Table 2. Power Signal Pin Listing (continued) Signal Connection Notes VDD 1.0 V ± 50 mV Core supply voltage OVDD 3.3 V ± 300 mV Standard I/O voltage NOTE All the power pins need to be tied to their corresponding voltages irrespective of the fact that a module is used or not in the system. Design Checklist for PowerQUICC II Pro MPC8309 Processor, Rev. 1 6 Freescale Semiconductor
4 Clocking Figure 3 shows the internal distribution of clocks within the MPC8309. SYS_XTAL_OUT CRYSTAL SYS_XTAL_IN SYS_CLK_IN CFG_CLKIN_DIV QE_CLK_IN MPC8309 Rest of the System /n System PLL PCI Clock Divider csb_clk Clock Unit csb_clk to rest of the device e300c3 core Core PLL ddr_clk lbc_clk to DDR memory controller core_clk DDR Clock Divider /2 qe_clk QE PLL CLK Gen QE Block Figure 3. Clock Subsystem Block Diagram for MPC8309 Design Checklist for PowerQUICC II Pro MPC8309 Processor, Rev. 1 LCLK[0:1] Clocking Local Bus Memory Device Freescale Semiconductor 7 /n to local bus LBC Clock Divider MEMC_MCK MEMC_MCK PCI_SYNC_IN PCI_SYNC_OUT PCI_CLK[0:2] DDR Memory Device
Page 1 and 2: Freescale Semiconductor Application
Page 3 and 4: atings only and functional operatio
Page 5: 2.6 PLL Power Supply Filtering Desi
Page 9 and 10: Design Checklist for PowerQUICC II
Page 15 and 16: From Target Board Sources (if any)
Page 17 and 18: Table 7 summarizes the DDR SDRAM pi
Page 21 and 22: 7.3 PCI Bus Interface Design Checkl
Page 23 and 24: Signal PCI_GNT[0] I/O External arbi
Page 25 and 26: Signal Pin Type USBDR_TXDRXD[3]/ GP
Page 27 and 28: 7.6 DUART Table 13 lists the dual U
Page 29 and 30: 7.9 QUICC Engine Communication Inte
Page 31 and 32: Signal Pin Type FEC2_RXD[3] / GPIO[
Page 33 and 34: 7.9.2 HDLC/TDM Ports The QUICC Engi
Page 35 and 36: Signal Pin Type SD_CD I As needed +
Page 37: How to Reach Us: Home Page: www.fre

Design Checklist for PowerQUICC II Pro MPC8309 Processor

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