Design Checklist for PowerQUICC II Pro MPC8309 Processor

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Functional Blocks Table 9 summarizes the local bus pins. Signal Pin Type Table 9. Local Bus Pin Listing Connection If Used If Not Used LAD[0:15] I/O As needed Open — LA[16:25] O As needed Open — LCS[0:3] O As needed Open — LWE/LFWE/ LBS O As needed Open — LBCTL O As needed Open — LALE O As needed Open — LGPL0/LFCLE O As needed Open — LGPL1/LFALE O As needed Open — LGPL2/LFRE/LOE O As needed Open — LGPL3/LFWP O As needed Open — LGPL4/LGTA/LUPWAIT/LFRB I/O As needed 4.7k� – 10k� to OVDD Design Checklist for PowerQUICC II Pro MPC8309 Processor, Rev. 1 20 Freescale Semiconductor Notes Output when configured as LGPL4. LGPL5 O As needed Open — LCLK[0:1] O As needed Open — Note: Refer to Table 13 for LCS[4:7].
7.3 PCI Bus Interface Design Checklist for PowerQUICC II Pro MPC8309 Processor, Rev. 1 Functional Blocks The reset configuration word high controls the hardware configuration of the PCI blocks as follows: • RCWH[PCIHOST]— Host/agent mode for PCI • RCWH[PCIARB]—PCI internal/external arbiter mode select. As Table 10. shows, signals of the PCI interface are multiplexed with the CompactPCI Hot Swap pins. Either PCI or Hot Swap functionality is selected by the RCWH[PCIARB] bit setting. When an external arbiter is selected (RCWH[PCIARB] = 0), the CompactPCI Hot Swap pins function. When an internal arbiter is selected (RCWH[PCIARB] = 1), the GNTx/REQx pins function. Refer to the MPC8309 PowerQUICC II Pro Integrated Host Processor Family Reference Manual for details on the reset configuration word high settings. Signal Pin Type If Used Table 10. PCI Bus Interface Pin Listing Connection PCI_INTA O 2 k–10 k� to OV DD If Not Used Freescale Semiconductor 21 Notes Open Open drain signal. In agent mode, INTA typically connects to a central interrupt controller. PCI_RESET_OUT O As needed Open This signal is used only in host mode. It must be left unconnected in agent mode. PCI_AD[31:0] I/O As needed 2 k–10 k� to OV DD or Open PCI_C / BE[3:0] I/O As needed + 2 k–10 k� to OV DD 2 k–10 k� to OV DD or Open PCI_PAR I/O As needed 2 k–10 k� to OV DD PCI_FRAME I/O As needed + 2 k–10 k� to OV DD PCI_TRDY I/O As needed + 2 k–10 k� to OV DD PCI_IRDY I/O As needed + 2 k–10 k� to OV DD 2 k–10 k� to OV DD 2 k–10 k� to OV DD 2 k–10 k� to OV DD If the PCI port is not used, no termination is needed if the bus is parked. Software needs to park the bus as follows: 1. RCWHR[PCIHOST] = 1 2. RCWHR[PCIARB] = 1 3a. PCI Arbiter Control Configuration Register PM bit = 1, or 3b. PCI_GCR[BBR] = 1 If the PCI port is not used, no termination is needed if the bus is parked. Software needs to park the bus as follows: 1. RCWHR[PCIHOST] = 1 2. RCWHR[PCIARB] = 1 3a. PCI Arbiter Control Configuration Register PM bit = 1, or 3b. PCI_GCR[BBR] = 1 If the PCI port is not used, this signal must be pulled up. PCI specification requires a weak pullup. PCI specification requires a weak pullup. PCI specification requires a weak pullup.
Page 1 and 2: Freescale Semiconductor Application
Page 3 and 4: atings only and functional operatio
Page 5 and 6: 2.6 PLL Power Supply Filtering Desi
Page 7 and 8: 4 Clocking Figure 3 shows the inter
Page 9 and 10: Design Checklist for PowerQUICC II
Page 15 and 16: From Target Board Sources (if any)
Page 17 and 18: Table 7 summarizes the DDR SDRAM pi
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Page 23 and 24: Signal PCI_GNT[0] I/O External arbi
Page 25 and 26: Signal Pin Type USBDR_TXDRXD[3]/ GP
Page 27 and 28: 7.6 DUART Table 13 lists the dual U
Page 29 and 30: 7.9 QUICC Engine Communication Inte
Page 31 and 32: Signal Pin Type FEC2_RXD[3] / GPIO[
Page 33 and 34: 7.9.2 HDLC/TDM Ports The QUICC Engi
Page 35 and 36: Signal Pin Type SD_CD I As needed +
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Design Checklist for PowerQUICC II Pro MPC8309 Processor

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