Design Checklist for PowerQUICC II Pro MPC8309 Processor

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Power Figure 1 shows a power sequencing example. 90% 2.4 Power Planes Figure 1. Power Sequencing Example Each V DD pin of the MPC8309 must be provided with a low-impedance path to the board power supply. Similarly, each ground pin must be provided with a low-impedance path to ground. The power supply pins drive distinct groups of logic on-chip. The capacitor leads and associated printed-circuit traces connecting to chip V DD and ground must be kept to less than half an inch per capacitor lead. 2.5 Decoupling PORESET I/O Voltage (GVDD, OVDD) Core Voltage (VDD) >= 32 X tSYS_CLK_IN clocks Due to large address and data buses and high operating frequencies, the MPC8309 can generate transient power surges and high-frequency noise in its power supply, especially while driving large capacitive loads. This noise must be prevented from reaching other components in the system, and it requires a clean, tightly regulated source of power. Therefore, the system designer should place at least one decoupling capacitor at each V DD , GV DD and OV DD pin. These decoupling capacitors should receive their power from separate V DD , GV DD , OV DD , and GND power planes in the PCB, using short traces to minimize inductance. Capacitors can be placed directly under the device using a standard escape pattern. Other capacitors can surround the part. These capacitors should have a value of 0.01 or 0.1 �F. Only ceramic surface mount technology (SMT) capacitors must be used to minimize lead inductance. Additionally, several bulk storage capacitors must be distributed around the PCB, feeding the V DD , GV DD , and OV DD planes, to enable quick recharging of the smaller chip capacitors. These bulk capacitors should have a low equivalent series resistance (ESR) rating to ensure quick response time. They should also connect to the power and ground planes through two vias to minimize inductance. Suggested bulk capacitors: 100–300 �F. Use simulation to minimize noise on the power supplies before proceeding into the PCB design and manufacturing stage of development. Design Checklist for PowerQUICC II Pro MPC8309 Processor, Rev. 1 4 Freescale Semiconductor 0.7 V
2.6 PLL Power Supply Filtering Design Checklist for PowerQUICC II Pro MPC8309 Processor, Rev. 1 Pin Listing and Connections Each PowerQUICC II Pro PLL gets power through independent power supply pins (AVDD1, AVDD2, and AVDD3). The AVDD level should always equal VDD , and preferably be derived directly from VDD through a low pass filter scheme. There are several reliable ways to provide power to the PLLs, but the recommended solution is to use independent filter circuits as illustrated in Figure 2, one to each of the three AVDD pins, thus reducing noise injection from one PLL to the other. This circuit filters noise in the PLL resonant frequency range from 500 kHz to 10 MHz. It must be built with SMT capacitors with a minimum effective series inductance (ESL). Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are recommended instead of a single large value capacitor. Place each circuit as closely as possible to the specific AVDD pin being supplied to minimize noise coupled from nearby circuits. It must be possible to route directly from the capacitors to the AVDD pin without the inductance of vias. Figure 2 shows the PLL power supply filter circuit for System PLL(AV DD1 ), QE PLL(AV DD2 ), and Core PLL (AV DD3 ). V DD 10�� Figure 2. PLL Power Supply Filter Circuit 3 Pin Listing and Connections Table 2 summarizes the power signal pins. 2.2 µF 2.2 µF Table 2. Power Signal Pin Listing Signal Connection Notes AV DD1 1.0 V ± 50 mV Analog power for e300 core PLL AV DD2 1.0 V ± 50 mV Analog power for system PLL AV DD3 1.0 V ± 50 mV Analog power for QE PLL GV DD 1.8 V ± 100 mV DDR2 I/O voltage MVREF 0.49xGV DD to 0.51 xGV DD DDR reference voltage AV DD1 AV DD2and AV DD3 Low ESL Surface Mount Capacitors Freescale Semiconductor 5
Page 1 and 2: Freescale Semiconductor Application
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Page 7 and 8: 4 Clocking Figure 3 shows the inter
Page 9 and 10: Design Checklist for PowerQUICC II
Page 15 and 16: From Target Board Sources (if any)
Page 17 and 18: Table 7 summarizes the DDR SDRAM pi
Page 21 and 22: 7.3 PCI Bus Interface Design Checkl
Page 23 and 24: Signal PCI_GNT[0] I/O External arbi
Page 25 and 26: Signal Pin Type USBDR_TXDRXD[3]/ GP
Page 27 and 28: 7.6 DUART Table 13 lists the dual U
Page 29 and 30: 7.9 QUICC Engine Communication Inte
Page 31 and 32: Signal Pin Type FEC2_RXD[3] / GPIO[
Page 33 and 34: 7.9.2 HDLC/TDM Ports The QUICC Engi
Page 35 and 36: Signal Pin Type SD_CD I As needed +
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Design Checklist for PowerQUICC II Pro MPC8309 Processor

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