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Alexander (Sandy) Marquardt, Vaughn Betz, and Jonathan Rose

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11. REFERENCES<br />

[1] S. Brown, R. Francis, J. <strong>Rose</strong>, <strong>and</strong> Z. Vranesic, Field-Programmable<br />

Gate Arrays, Kluwer Academic Publishers,<br />

1992.<br />

[2] Altera Inc., Data Book, 1998.<br />

[3] Xilinx Inc., “XC5200 Series of FPGAs”, Data Book, 1997.<br />

[4] Xilinx Inc., “Virtex 2.5 V Field Programmable Gate Arrays”,<br />

Advance Product Data Sheet, 1998.<br />

[5] S. Kaptanoglu et. al., “A new high density <strong>and</strong> very low cost<br />

reprogrammable FPGA Architecture”, FPGA, 1999, pp. 3 -<br />

12.<br />

[6] O. Agrawal et. al., “An Innovative, Segmented High Performance<br />

FPGA Family with Variable-Grain-Architecture <strong>and</strong><br />

Wide-gating Functions,” FPGA, 1999, pp. 17 - 26.<br />

[7] V.<strong>Betz</strong> <strong>and</strong> J. <strong>Rose</strong>, “How Much Logic Should Go in an<br />

FPGA Logic Block?,” IEEE Design <strong>and</strong> Test Magazine,<br />

Spring 1998, pp. 10-15.<br />

[8] V. <strong>Betz</strong>, “Architecture <strong>and</strong> CAD for Speed <strong>and</strong> Area Optimization<br />

of FPGAs,” Ph. D. Dissertation, University of Toronto,<br />

1998.<br />

[9] V. <strong>Betz</strong>, J. <strong>Rose</strong>, A. <strong>Marquardt</strong>, Architecture <strong>and</strong> CAD for<br />

Deep-Submicron FPGAs, Kluwer Academic Publishers, February<br />

1999.<br />

[10] A. <strong>Marquardt</strong>, V. <strong>Betz</strong>, J. <strong>Rose</strong>, “Using Cluster-Based Logic<br />

Blocks <strong>and</strong> Timing-Driven Packing to Improve FPGA Speed<br />

<strong>and</strong> Density”, FPGA, 1999, pp 37-46.<br />

[11] S. Yang, “Logic Synthesis <strong>and</strong> Optimization Benchmarks,<br />

Version 3.0,” Tech. Report, Microelectronics Center of North<br />

Carolina, 1991.<br />

[12] E. M. Sentovich et al, “SIS: A System for Sequential Circuit<br />

Analysis,” Tech. Report No. UCB/ERL M92/41, University<br />

of California, Berkeley, 1992.<br />

[13] J. Cong <strong>and</strong> Y. Ding, “Flowmap: An Optimal Technology<br />

Mapping Algorithm for Delay Optimization in Lookup-Table<br />

Based FPGA Designs,” IEEE Trans. on CAD, Jan. 1994, pp<br />

1-12.<br />

[14] A. <strong>Marquardt</strong>, “Cluster-Based Architecture, Timing-Driven<br />

Packing, <strong>and</strong> Timing-Driven Placement for FPGAs,”<br />

M.A.Sc., University of Toronto, 1999.<br />

[15] S. Kirkpatrick, C. Gelatt <strong>and</strong> M. Vecchi, “Optimization by<br />

Simulated Annealing,” Science, May 13, 1983, pp. 671 - 680.<br />

[16] C. Sechen <strong>and</strong> A. Sangiovanni-Vincentelli, “The TimberWolf<br />

Placement <strong>and</strong> Routing Package,” JSSC, April 1985, pp. 510<br />

- 522.<br />

[17] C. Sechen <strong>and</strong> K. Lee, “An Improved Simulated Annealing<br />

Algorithm for Row-Based Placement,” ICCAD, 1987, pp.<br />

478 - 481.<br />

[18] W. C. Elmore, “The Transient Response of Damped Linear<br />

Networks with Particular Regard to Wideb<strong>and</strong> Amplifiers,”<br />

J. Applied Physics, Vol. 19, January 1948, pp. 55-63.<br />

[19] T. Okamoto <strong>and</strong> J. Cong, “Buffered Steiner Tree Construction<br />

with Wire Sizing for Interconnect Layout Optimization,”<br />

ICCAD, 1996, pp. 44 - 49.<br />

[20] J. <strong>Rose</strong>, R. J. Francis, D. Lewis <strong>and</strong> P. Chow, “Architecture<br />

of Programmable Gate Arrays: The Effect of Logic Block<br />

Functionality on Area Efficiency,” IEEE Journal of Solid<br />

State Circuits, Oct. 1990, pp. 1217 - 1225.<br />

[21] J. <strong>Rose</strong> <strong>and</strong> S. Brown. “Flexibility of Interconnection Structures<br />

for Field-Programmable Gate Arrays,” JSSC, March<br />

1991, pp. 277 - 282.

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