ZTE Communications

R esearch Papers
A Histogram-Based Static Error Correction Technique for Flash ADCs: Implementation
J Jacob Wikner, Armin Jalili, Sayed Masoud Sayedi, and Rasoul Dehghani
I CP+ΔI1
I CP+ΔI2
VDD
▲Figure 1. Triangular signal generator (TSG) circuit with error sources
indicated.
MUX are connected to the interval detector block, which
determines which intervals, Ii (i = 1, 2, ...,16), the sampled
value belongs to. The counter records the number of samples
for each Ii. The ideal number of samples for each interval can
be calculated in advance because the input PDF must be
known.
The estimation block in the ADC estimates the voltage
errors by comparing the wanted (ideal) number of samples,
~
Ni, and the recorded number of samples, Ni (the tilde
indicates the non-ideal case), for each Ii. The results of the
comparison are then used by the trimming block to
compensate for static errors. As we outlined in the
behavioral-level description in [1], the trimming block can
compensate for ADC errors by adjusting the voltage taps of
the resistor ladder. This changes the ADC reference levels
generated by the reference-selection block.
3 PDF Generator Circuit
The PDF generator is a vital component because it creates
a reference signal with a known PDF, which the calibration
relies on. Various analog signals might be used for test
purposes, but a good candidate in terms of implementation
complexity is the ramp function, which can be generated with,
for example, a charge pump. Ideally, the ramp signal has a
uniform distribution; that is, the PDF has a constant value
because the ramp takes all analog levels with equal
probability. For our ADC, we use a triangular signal generator
(TSG) (Fig. 1) for uniform distribution. (We will return to the
choppers and MUXs in Fig. 1.) The capacitor, CCP , is charged
and discharged sequentially by a pull-up or pull-down
current, ICP. Two comparators toggle the direction of the
charge pump (up or down) with the help of a decoder and a
latch. The overall circuit is a fixed-frequency oscillator.
The resulting triangular wave has amplitude of V REF and a
constant PDF. Ideally, the TSG range should be the same as
the ADC range, that is, V REF = VR. The signal must be kept in
the range [-VR, VR] and should vary linearly with time. Other
signal specifications do not need to be taken into account;
slope variation, for example, does not affect the PDF
distribution. However, in the TSG circuit (Fig. 1), some
potentially dominating non-ideal effects are mismatch
64
CCP+ΔCCP
VREF
-VREF
VOS, tsg1
VOS, tsg2
Chopper
S
Chopper
ZTE COMMUNICATIONS
S
τt
M
U
X
S
M
U
X
March 2012 Vol.10 No.1
S
Bistable Circuit
T-Flip Flop
between up and down currents, variation in capacitance,
comparator offset, and transition delay.
Of these parameters, the current mismatch, ΔICP, and
capacitor mismatch, ΔCCP, only change the slopes of the
generated ramps and therefore do not affect the PDF. The
offset delay, V os,tsg, and transition delay, τt, change the upper
and lower limits of the voltage across the capacitor. This
means there is a deviation from the peak values VREF and -VREF.
This variation can be determined from the resolution of the
PDF circuit, and its maximum value is given by
V LSB, tsg=V OS, tsg+τt (ICP/CCP) (1)
where VLSB,tsg is the voltage of the least-significant bit (LSB) in
the TSG circuit. The TSG resolution, n tsg, is
n tsg= log2 (2VREF/VLSB,tsg) (2)
Substituting VLSB,tsg from (1) into (2) gives
2VREF
n tsg= log2 (3)
V OS, tsg+τt(ICP/CCP)
The voltage across the capacitor forms the output of the
TSG circuit and is fed to the ADC during calibration. The ratio
between the TSG frequency and ADC sampling frequency
should be carefully chosen to guarantee a uniform distribution
[2], [3].
Assuming the TSG is nonlinear, we can start by looking at
first-order, non-linear transfer characteristics. The linearity
can be specified by the maximum deviation from a straight
line between the two end points, VREF and -VREF. The deviation,
η, is normalized with respect to the signal swing and is
expressed as a percentage:
η = (ΔVmax/2VREF)·100 (4)
where ΔVmax is the maximum deviation from the straight line.
Typically, this deviation is due to limited output impedance of
the current sources, and a voltage-dependent capacitance,
C CP. To determine the effects of TSG errors on calibration, a
behavioral-level model of the TSG is used for simulation.
Starting with a 4-bit flash ADC and large comparator offsets
(σ is approximately 60 mV for VR = 1 V ), we run Monte Carlo
analyses and calibrate the ADC using equations (4)-(7) in [1].
The ADC differential nonlinearity (DNL) is extracted and
characterized with respect to the maximum, non-ideal
deviation from (4).
The simulation results are shown in Fig. 2. The DNL is
expressed in LSBs, and refers to a 4-bit converter. DNL
should therefore be below 0.5 LSB for full, nominal accuracy.
In Fig. 2, an 8-bit resolution is indicated. In practical design,
the nonlinear behavior of the TSG circuit is not significant, and
the nonlinearity as high as four or five percent can be
tolerated.
However, for high-resolution converters, a large n tsg is
required. In this case, (3) imposes stricter limitations on Vos,tsg
and τ t, and for each extra bit, we halve the accepted values.
The design of a comparator with small offset and low delay
could become quite complex, and to avoid this, we introduce
a chopping technique that cancels out the effect of the offset