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ADC Output Decimal Value (mV) 0.15 0.10 0.05 0 -0.05 -0.10 VR -VR -0.15 DNL=1.2 LSB DNL=1.5 LSB DNL=1.4 LSB DNL=1.6 LSB DNL=0.9 LSB DNL=0.3 LSB DNL=0.13 LSB DNL=0.16 LSB -0.20 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 Time (μs) ADC: analog-to-digital converter DNL: differential nonlinearities ▲Figure 6. Transistor-level simulations showing calibration steps and compensation for T/H kickback errors. ADC Reference Voltage Levels (V) 0.75 0.70 0.65 0.60 0.55 0.50 0.45 0 0.2 Upper Level of Signal Range Lower Level of Signal Range 0.4 0.6 0.8 Time (μs) 1.0 1.2 ADC: analog-to-digital converter ▲Figure 7. Calibration steps showing the compensation for T/H gain error. can isolate the gain error. Fig. 7 shows the arrangement of the reference voltages of the ADC during calibration. At first, the reference levels are in their ideal positions. As the calibration proceeds, these reference levels are pushed towards the range of the T/H output. The original ADC range is shown by the dotted line, and the reference levels are pushed and distributed inside the signal range. Each 0.2 μs corresponds to one calibration step. 4.3 Distortion and Nonlinearity Dominant T/H errors include distortion that are due to nonlinearity of the sample-and-hold capacitor. Switch-on resistance is another dominant T/H error. The calibration here is not intended to compensate for any dynamic nonlinear errors. For static errors, the input and output relationship can be described by a relatively well-defined polynomial: 2 3 vout= a0+a1vin+a2vin+a3vin+… (17) The T/H static nonlinearity can be calibrated as long as the ai coefficients are small enough. To determine the effect of moderate distortion, the T/H is used in an 8-bit flash ADC. Behavioral-level comparators are used, and the sampling switch is bypassed to avoid kickback. The effect of distortion can then be analyzed in isolation. INL before calibration in Fig. 8(a) has a maximum absolute value of about 2 LSB. INL after calibration in Fig. 8(b) and is improved to about 0.15 LSB. 5 Implementation Fig. 9 shows the proposed calibration system, and an 1.4 1.6 implementation of the calibration algorithm has already been presented in [1]. The ADC input is connected to the TSG circuit (PDF generator) in calibration mode [1]. The 2 n -1 comparators produce a thermometer code so that an ADC level is represented by a set of r consecutive 1s at the bottom and s consecutive 0s at the top. The MUX selects a set of 16 comparators and feeds their outputs to the interval-detector block. This block then locates the input signal in the different voltage intervals and produces a 1-of-16 (walking-one) code at the block’s output, which indicates the corresponding code value. For small errors, the voltage intervals do not overlap [1], and in the thermometer code, there are normal transitions between 1 and 0, that is, no sparkle errors. However, for large offset errors, the intervals overlap, and this is detected and compensated for by the interval-detector block. The outputs of the interval detector are applied to the estimation block, which contains an array of counters that record the number of samples belonging to each interval. All offset values are then estimated according to the procedure given in the behavioral-level description of the algorithm [1]. The estimated offset values are stored in a 16-word RAM. Each word represents the offset of a comparator in the chosen set. The trimming block in Fig. 9 reads the RAM and performs encoding to reduce the word length. It then stores the result in registers that contain 2 n -1 words that represent the offset for each comparator. The register word lengths typically depend on the maximum comparator offset because larger offsets result in longer word lengths. Each register defines the select lines, which in turn control the analog multiplexers (AMUXs) in the reference generator. There is one AMUX assigned to each comparator. Each MUX INL of the T/H in an 8-bit Flash ADC (LSB) INL of the T/H in an 8-bit Flash ADC (LSB) 0.5 0 -0.5 -1 -1.5 -2 -2.5 0 0.05 0 -0.05 -0.1 -0.15 -0.2 0 20 40 50 60 80 100 100 120 Code (a) Code (b) R esearch Papers A Histogram-Based Static Error Correction Technique for Flash ADCs: Implementation J Jacob Wikner, Armin Jalili, Sayed Masoud Sayedi, and Rasoul Dehghani ADC: analog-to-digital converter INL: integral nonlinearities T/H: track-and-hold ▲Figure 8. INL of an 8-bit flash converter using a T/H circuit (a) before and (b) after calibration. 150 140 Before Calibration 160 After Calibration 200 180 200 250 March 2012 Vol.10 No.1 <strong>ZTE</strong> COMMUNICATIONS 67
R esearch Papers A Histogram-Based Static Error Correction Technique for Flash ADCs: Implementation J Jacob Wikner, Armin Jalili, Sayed Masoud Sayedi, and Rasoul Dehghani V in TSG PDF Generator Reference Generator Comparator Array T/H Register File (2 n -1) Word Register File MUX: multiplexer PDF: probability density function ▲Figure 9. Proposed calibration system. T/H: track-and-hold TSG: triangular signal generator can select from a batch of reference voltage taps on the resistor ladder. Each input provides a fractional LSB so that a fine voltage step can be added to or subtracted from the MUX output. This output is then used as the new reference voltage for the corresponding comparator. 5.1 Complexity The analog switch area of the AMUX array is proportional to where n is the resolution of the converter, V os,max is the maximum static error amplitude covered by the calibration algorithm, V LSB is the LSB voltage, M is the number of fine sub-LSB steps, and A ATG is the area of each TG. Inserting V LSB = 2V R / 2 n into (18) results in The same equation can be used for the decoder part: the digital MUX (DMUX) array at the output of the comparators is implemented using unity TGs. In this case, the area can be approximated using where A DTG is the area of the unity TG. The register file contains 2 n -1 words, and each represents the selected lines of the corresponding AMUX. So, similar to (19), we get where A L is the area of a typical latch used in the register file. According to (19)-(21), the areas of the AMUX, DMUX, and register file grow exponentially in relation to resolution n. The size of the remaining calibration blocks is proportional to the resolution because of the segmented approach [1]. With the segmented approach, a considerable amount of calibration hardware grows linearly, rather than exponentially, in relation to converter resolution. M U X Trimming Decoder R A M D out MUX Array Interval Detector 16-Word RAM Estimation A ASW = (2 n 2V os,max -1)· ·A ATG (18) V LSB/M A ASW A ATG = (2 n -1)·2 n V os,max ·M· (19) V R A DSW/A DTG = 2 n -1 (20) A Reg A L 68 = (2 n 2 -1)·log2 (21) n MV OS, max V R <strong>ZTE</strong> COMMUNICATIONS March 2012 Vol.10 No.1 The size of the calibration blocks can be ordered according to the size of the total ADC area: all-digital estimation block, RAM, and trimming block (33%); decoder part of the AMUX array (10%); analog switches of the AMUX array (6%); TSG circuit (2%); register file (2%); and DMUX array (1%). This accounts for approximately half the total area of the ADC, which is 0.25 mm 2 . Unlike the analog area, the calibration area does not scale exponentially as higher resolutions are attained. Using calibration, the analog comparator area can be kept fairly low and, most importantly, analog complexity can be reduced by using standard digital cells. 6 Simulation Results As a proof-of-concept, a single-ended, 5-bit flash ADC is designed in the same 1.2 V, 65 nm CMOS process used previously. The ADC range is from 475 to 725 mV, which allows a full range of 250 mV (related to the single-ended signal). Fig. 10 shows the T/H circuit where a boot-strapped sample switch is used to enhance performance [6]. A replica of the input buffer injects the test signal, Vtest, during calibration. A transmission gate (M3 and M4) is used as a switch to inject the test signal. The gate can be small; in this design it is 25 times smaller than the sample switch, Msw, because the test signal is typically low-frequency. Therefore, the additional parasitic capacitance is small, and the dynamic performance of the T/H remains relatively unaffected. The T/H circuit has a gain loss of approximately -1.7 dB. Fig. 11 shows the ADC reference generator circuit adopted from [7]. A replica of the T/H circuit is used to match the common-mode level of the reference generator with the input signal. A version of the T/H, scaled down 40 times, is used. Corner and Monte Carlo analyses show that the replica matches the original T/H well within one LSB. Any residual errors due to the mismatch are, however, compensated for during calibration. The test signal is generated using the TSG circuit in Fig. 1. Vtest M R1 Vin VDD VB Bootstrapped Switching Φ2 Φ1 Φ2 Φ2 VDD ▲Figure 10. T/H circuit and injection of the test signal. Φ1 VDD M1 MSW M2 C H Φcal -Φcal M 3 M 4 Φcal Replica of Input Buffer Calibration Normal Mode Φ1 Φ2 Vout
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