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A Histogram-Based Static Error Correction Technique for Flash ADCs: Implementation
J Jacob Wikner, Armin Jalili, Sayed Masoud Sayedi, and Rasoul Dehghani
structure (Fig. 10) is an active, source-follower-based T/H. It
contains input buffers implemented by NMOS
source-followers as well as output buffers implemented by
PMOS source-followers. The NMOS drives the
sample-and-hold capacitor, CH, and the PMOS drives the
comparator inputs that form a potentially large capacitive load.
4.1 Kickback Noise
Kickback noise due to the capacitive coupling from
comparator output to input affects both the references and
signal inputs. In [1], we observed that by adding trimming
switches, some of the kickback noise was suppressed onto
the reference ladder. However, a T/H circuit with high driving
capability (low enough output impedance) is required to
diminish kickback on its own output (the comparator inputs).
Calibration relaxes design requirements by compensating
for the static part of kickback noise. This can be done by
assuming each comparator has zero offset error. The
kickback noise on each comparator input is not detrimental
unless the input signal is close to the corresponding reference
voltage, that is, when the comparator makes a decision. From
the point of view of static, kickback noise is deterministic and
can be modeled by an equivalent offset voltage at each
comparator. However, the amplitude does not depend solely
on the input signal; it also depends on its derivative(s). In
practice, the amount of kickback noise changes with
frequency. To determine the effects of kickback noise in
practice, a T/H circuit is designed in a 1.2 V, 65 nm CMOS
process and used in a 4-bit flash ADC.
Fig. 5 shows deviation of kickback noise from the average
for 15 reference levels. The signal frequency (full-scale
sinusoid) is swept, and to isolate kickback noise from other
errors—including clock feedthrough (CFT) and charge
injection—the sampling switch is bypassed (its drain and
source are tied together). Up to about 10 MHz, kickback noise
is nearly constant and depends only on the input signal levels.
For frequencies higher than 100 MHz, kickback noise
amplitude increases significantly. For low frequencies,
deviation from the average is nearly constant, which means
that the calibration algorithm can calibrate the static part of
the kickback noise.
For simplicity, we assume the kickback noise for all levels
i = 1, 2,...,2 n -1 changes in proportion to the input signal level,
given by
v k,i(v in) = α ivin + βi
where v k,i is the kickback amplitude, v in is the input signal level
and αi and βi are constants. In the first calibration step, the
estimated comparator offset i is
v est1,i = Vk,i (Vr,i ) =α iVr,i + βi
where v est1,i is the estimated offset value and Vr,i is the
reference level, which can be used as an approximation of the
input signal level. v est1,i is added to the reference level by the
trimming circuitry [1] and compensates for the offset. The
second calibration step gives
v est2,i = Vk,i (Vr,i +v est1,i)-v est1,i =α i 2 Vr,i +α iβi
(13)
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ZTE COMMUNICATIONS
March 2012 Vol.10 No.1
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Deviation from the Average
Kickback Amplitude )mV)
15
10
5
0 10 0
10 1
▲Figure 5. Deviation of kickback amplitude from its average versus
input signal frequency.
and the mth calibration step gives
Input Frequency (MHz)
m m-1
v estm,i = α i Vr,i +α i βi (14)
For a nonzero comparator offset, the trip point is shifted
from Vr,i to Vr,i-VOS,i, and (14) is modified as
mm m m-1
v estm,i = α i (1-α i)VOS,i +α iVr,i +α i βi (15)
For a typical T/H circuit, we assume that α i is less than 1
because it is very unlikely the kickback noise is in parity with
high input signal levels. This means that the kickback
amplitude of the ith comparator is less than the corresponding
reference level. In this case, as m increases with calibration
iterations, the estimated voltage v estm,i in (15) decreases. The
calibration converges and compensates for the static part of
the kickback noise.
To verify (15), we examine a 4-bit flash ADC implemented
in a 65 nm CMOS process with the previously mentioned
parameters. To focus solely on the kickback noise, the
nominal condition is simulated with zero mismatch. The T/H is
omitted, and source impedance is introduced into the input
signal generator in order to determine kickback behavior. The
ADC response to a full-scale ramp signal is shown in Fig. 6.
Each ramp corresponds to one calibration step. Before
calibration (the first ramp), the ADC suffers DNL errors and
missing codes because of the kickback noise. After seven
calibration steps, the algorithm converges and compensates
for the kickback noise.
4.2 Gain Errors
Another issue with T/H circuits is gain error. Some effort is
required to design a buffer with acceptable gain variations,
especially in fine-line CMOS technologies where process
variations can substantially affect the open-loop buffer gain.
Using the proposed technique, gain error can be calibrated
because the effect of the gain error can be described by a set
of comparator offset voltages. The corresponding reference
and trimming voltages are then rearranged to compensate for
the gain error. The T/H gain error in the calibration algorithm
generates equivalent offset errors given by
v OS,i = -γv r,i
where γ is the gain error of the T/H circuit.
The T/H circuit is used in a 4-bit flash ADC, and
behavioral-level models are used so that the comparators
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