Infineon SAB 80C517A, SAB 83C517A-5 User's Manual ... - Keil

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Table 3-1, Special Function Register (cont´d) Semiconductor Group 3 - 6 Memory Organization Block Symbol Name Address Contents after Reset XRAM XPAGE SYSCON CPU ACC B DPH DPL DPSEL PSW SP A/D- Converter Interrupt System MUL/DIV Unit Compare/ Capture- Unit (CCU), Timer2 ADCON0 ADCON1 ADDATH ADDATL IEN0 CTCON 2) IEN1 IEN2 IP0 IP1 IRCON0 IRCON1 TCON 2) T2CON 2) ARCON MD0 MD1 MD2 MD3 MD4 MD5 CCEN CC4EN CCH1 CCH2 CCH3 CCH4 CCL1 Page Address. Reg. for extended onchip RAM XRAM Control Reg. Accumulator B-Register Data Pointer, High Byte Data Pointer, Low Byte Data Pointer Select Register Program Status Word Register Stack Pointer A/D Converter Control Register 0 A/D Converter Control Register 1 A/D Converter Data Register High Byte A/D Converter Data Register Low Byte Interrupt Enable Register 0 Com. Timer Control Register Interrupt Enable Register 1 Interrupt Enable Register 2 Interrupt Priority Register 0 Interrupt Priority Register 1 Interrupt Request Control Register Interrupt Request Control Register Timer Control Register Timer 2 Control Register Arithmetic Control Register Multiplication/Division Register 0 Multiplication/Division Register 1 Multiplication/Division Register 2 Multiplication/Division Register 3 Multiplication/Division Register 4 Multiplication/Division Register 5 Comp./Capture Enable Reg. Comp./Capture 4 Enable Reg. Comp./Capture Reg. 1, High Byte Comp./Capture Reg. 2, High Byte Comp./Capture Reg. 3, High Byte Comp./Capture Reg. 4, High Byte Comp./Capture Reg. 1, Low Byte 1) Bit-addressable special function registers 2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks. 3) X means that the value is indeterminate 91 H B1 H E0 H 1) F0 H 1) 83 H 82 H 92 H D0 H 1) 81 H D8 H 1) D H D9 H DA H A8 H 1) E1 H B8 H 1) 9A H A 9H B9 H C0 H 1) D1 H 88 H 1) 0C8 H 1) EF H E9 H EA H EB H EC H ED H EE H C1 H C9 H C3 H C5 H C7 H CF H C2 H 00 H XXXX XX01 B 3) 00 H 00 H 00 H 00 H XXXXX000 B 3) 00 H 07 H 00 H 00 H 00 H 00 H 00 H 0X00 0000 B 3) 00 H XX00 00X0 B 3) 00 H XX00 0000 B 00 H 00 H 00 H 00 H 0XXX XXXX B XX H XX H XX H XX H XX H XX H 00 H 00 H 00 H 00 H 00 H 00 H 00 H
Table 3-1, Special Function Register 1) Bit-addressable special function registers Semiconductor Group 3 - 7 Memory Organization Block Symbol Name Address Contents after Reset Compare/ Capture- Unit (CCU) (cont´d) CCL2 CCL3 CCL4 CMEM CMH0 CMH1 CMH2 CMH3 CMH4 CMH5 CMH6 CMH7 CML0 CML1 CML2 CML3 CML4 CML5 CML6 CML7 CMSEL CRCH CRCL COMSETL COMSETH COMCLRL COMCLRH SETMSK CLRMSK CTCON CTRELH CTRELL TH2 TL2 T2CON 2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks. 3) X means that the value is indeterminate Comp./Capture Reg. 2, Low Byte Comp./Capture Reg. 3, Low Byte Comp./Capture Reg. 4, Low Byte Compare Enable Register Compare Reg. 0, High Byte Compare Reg. 1, High Byte Compare Reg. 2, High Byte Compare Reg. 3, High Byte Compare Reg. 4, High Byte Compare Reg. 5, High Byte Compare Reg. 6, High Byte Compare Reg. 7, High Byte Compare Register 0, Low Byte Compare Register 1, Low Byte Compare Register 2, Low Byte Compare Register 3, Low Byte Compare Register 4, Low Byte Compare Register 5, Low Byte Compare Register 6, Low Byte Compare Register 7, Low Byte Compare Input Select Com./Rel./Capt. Reg. High Byte Com./Rel./Capt. Reg. Low Byte Compare register, Low Byte Compare register, High Byte Compare register, Low Byte Compare register, High Byte mask register, concerning COMSET mask register, concerning COMCLR Com. Timer Control Reg. Com. Timer Rel. Reg., High Byte Com. Timer Rel. Reg., Low Byte Timer 2, High Byte Timer 2, Low Byte Timer 2 Control Register C4 H C6 H CE H F6 H D3 H D5 H D7 H E3 H E5 H E7 H F3 H F5 H D2 H D4 H D6 H E2 H E4 H E6 H F2 H F4 H F7 H CB H CA H A1 H A2 H A3 H A4 H A5 H A6 H E1 H DF H DE H CD H CC H C8 H 1) 00 H 00 H 00 H 00 H 00 H 00 H 00 H 00 H 00 H 00 H 00 H 00 H 00 H 00 H 00 H 00 H 00 H 00 H 00 H 00 H 00 H 00 H 00 H 00 H 00 H 00 H 00 H 00 H 00 H 0X00 0000 B 3) 00 H 00 H 00 H 00 H 00 H
Page 1 and 2: Microcomputer Components SAB 80C517
Page 3 and 4: SAB 80C517A/83C517A-5 Revision Hist
Page 5 and 6: 1 Introduction The SAB 80C517A is a
Page 7 and 8: 2 Fundamental Structure The SAB 80C
Page 9 and 10: 3 Memory Organization Semiconductor
Page 11 and 12: 3.2 Data Memory Semiconductor Group
Page 13: Table 3-1, Special Function Registe
Page 17 and 18: 3.4 Architecture for the XRAM Semic
Page 19 and 20: Figure 3-2 Write Page Address to Po
Page 21 and 22: Figure 3-4 Use of Port 2 as I/O-Por
Page 23 and 24: 3.4.2 Control of XRAM in the SAB 80
Page 25 and 26: EA = 0 EA = 1 XMAP1, XMAP0 XMAP1, X
Page 27 and 28: Table 4-1, Status of all Pins Durin
Page 29 and 30: 4.2 Hardware Power Down Reset Timin
Page 31 and 32: Figure 4-2 Timing Diagram of Leavin
Page 33 and 34: 4.3 Fast internal Reset after Power
Page 35 and 36: Figure 4-4 Power-On of the SAB 80C5
Page 37 and 38: Semiconductor Group 5 - 2 On-Chip P
Page 39 and 40: Figure 5-1 10-Bit A/D-Converter Sem
Page 41 and 42: Special Function Register ADDATH, A
Page 43 and 44: 5.3 Additional Compare Mode for the
Page 45 and 46: Special Function Register CC4EN Bit
Page 47 and 48: Semiconductor Group 5 - 12 On-Chip
Page 53 and 54: Special Function Register SRELH, SR
Page 55 and 56: Detailled Description of the Oscill
Page 57 and 58: 6 Interrupt System 6.1 Additional I
Page 59 and 60: Special Function Register IRCON1 Bi
Page 61 and 62: 3.1 Priority Level Structure The fo
Page 63 and 64: 4 Device Specification Device Speci
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Logic Symbol Semiconductor Group 7-
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Pin Configuration (P-MQFP-100-2) Se
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Pin Definitions and Functions (cont
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Figure 1 Block Diagram Semiconducto
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Semiconductor Group 7-17 Device Spe
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s Table 1: Behaviour of P0/P2 and R
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Table 2 Special Function Register (
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Table 3 Special Function Registers
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Table 3 Special Function Registers
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Figure 4 Block Diagram A/D Converte
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Table 4 CCU Compare Configuration S
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Figure 6 Block Diagram of Timer 2 S
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Figure 9 Compare-Mode 2 (Port 5 onl
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Figure 10 Interrupt Structure of th
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Figure 10 Interrupt Structure of th
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Table 6 Performing a MDU-Calculatio
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Serial Interface 0 Serial Interface
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Figure 12 Functional Block Diagram
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ALE PSEN Port 0 Port 2 Program Memo
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AC Characteristics (cont’d) Exter
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ROM Verification Characteristics TA
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Application Circuitry for Verifying
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Package Outlines Plastic Package, P
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Infineon SAB 80C517A, SAB 83C517A-5 User's Manual ... - Keil

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