Infineon SAB 80C517A, SAB 83C517A-5 User's Manual ... - Keil

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Semiconductor Group 80C517A/83C517A-5 Contents Page 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 2 Fundamental Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 3 Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.1 Program Memory, ROM Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.2 Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.3 Special Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3.4 Architecture for the XRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 3.4.1 Accesses to XRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 3.4.2 Control of XRAM in the SAB 80C517A . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 3.4.3 Behaviour of Port0 and Port2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 4 System Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.1 Additional Hardware Power Down Mode in the SAB 80C517A . . . . . . . . . . 4-1 4.2 Hardware Power Down Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4.3 Fast internal Reset after Power-On . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 5 On-Chip Peripheral Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.1 Digital I/O Port Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.2 10-bit A/D-Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 5.3 Additional Compare Mode for the Concurrent Compare Unit . . . . . . . . . . . 5-8 5.4 New Baud Rate Generators for Serial Channel 0 and Serial Channel 1 . . 5-14 5.4.1 Serial Channel 0 Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14 5.4.2 Serial Channel 1 Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17 5.5 Modified Oscillator Watchdog Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19 6 Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 6.1 Additional Interrupt for Compare Registers CM0 to CM7 . . . . . . . . . . . . . . . 6-1 6.2 Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4 6.3 Priority Level Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5 7 Device Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
1 Introduction The SAB 80C517A is a superset of the high end microcontroller SAB 80C517. While maintaining all architectural and operational characteristics of the SAB 80C517 the SAB 80C517A incorporates more on-chip RAM as well as some enhancements in the compare / capture unit. The oscillator watchdog got an improved functionality. Also the operating frequency is higher than that of the SAB 80C517. SAB 80C517A / 83C517A-5 In this manual, any reference made to the SAB 80C517A applies to both versions, the SAB 80C517A and the SAB 83C517A-5, unless otherwise noted. Furthermore only new features of the SAB 80C517A in addition to the features of the SAB 80C517A/83C517A-5 are described. For additional reference, the user’s manual of the SAB 80C517/80C537 (Ord. No. B258-H6075-G1-X- 7600) should be used. Semiconductor Group 1 - 1 Introduction
Page 1 and 2: Microcomputer Components SAB 80C517
Page 3: SAB 80C517A/83C517A-5 Revision Hist
Page 7 and 8: 2 Fundamental Structure The SAB 80C
Page 9 and 10: 3 Memory Organization Semiconductor
Page 11 and 12: 3.2 Data Memory Semiconductor Group
Page 13 and 14: Table 3-1, Special Function Registe
Page 15 and 16: Table 3-1, Special Function Registe
Page 17 and 18: 3.4 Architecture for the XRAM Semic
Page 19 and 20: Figure 3-2 Write Page Address to Po
Page 21 and 22: Figure 3-4 Use of Port 2 as I/O-Por
Page 23 and 24: 3.4.2 Control of XRAM in the SAB 80
Page 25 and 26: EA = 0 EA = 1 XMAP1, XMAP0 XMAP1, X
Page 27 and 28: Table 4-1, Status of all Pins Durin
Page 29 and 30: 4.2 Hardware Power Down Reset Timin
Page 31 and 32: Figure 4-2 Timing Diagram of Leavin
Page 33 and 34: 4.3 Fast internal Reset after Power
Page 35 and 36: Figure 4-4 Power-On of the SAB 80C5
Page 37 and 38: Semiconductor Group 5 - 2 On-Chip P
Page 39 and 40: Figure 5-1 10-Bit A/D-Converter Sem
Page 41 and 42: Special Function Register ADDATH, A
Page 43 and 44: 5.3 Additional Compare Mode for the
Page 45 and 46: Special Function Register CC4EN Bit
Page 47 and 48: Semiconductor Group 5 - 12 On-Chip
Page 53 and 54: Special Function Register SRELH, SR
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Detailled Description of the Oscill
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6 Interrupt System 6.1 Additional I
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Special Function Register IRCON1 Bi
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3.1 Priority Level Structure The fo
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4 Device Specification Device Speci
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Logic Symbol Semiconductor Group 7-
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Pin Configuration (P-MQFP-100-2) Se
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Pin Definitions and Functions (cont
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Figure 1 Block Diagram Semiconducto
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Semiconductor Group 7-17 Device Spe
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s Table 1: Behaviour of P0/P2 and R
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Table 2 Special Function Register (
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Table 3 Special Function Registers
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Table 3 Special Function Registers
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Figure 4 Block Diagram A/D Converte
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Table 4 CCU Compare Configuration S
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Figure 6 Block Diagram of Timer 2 S
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Figure 9 Compare-Mode 2 (Port 5 onl
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Figure 10 Interrupt Structure of th
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Figure 10 Interrupt Structure of th
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Table 6 Performing a MDU-Calculatio
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Serial Interface 0 Serial Interface
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Figure 12 Functional Block Diagram
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ALE PSEN Port 0 Port 2 Program Memo
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AC Characteristics (cont’d) Exter
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ROM Verification Characteristics TA
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Application Circuitry for Verifying
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Package Outlines Plastic Package, P
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Infineon SAB 80C517A, SAB 83C517A-5 User's Manual ... - Keil

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