Infineon SAB 80C517A, SAB 83C517A-5 User's Manual ... - Keil

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5.2 10-bit A/D-Converter Semiconductor Group 5 - 3 On-Chip Peripheral Components In the SAB 80C517A is a new high performance / high speed 12-channel 10-bit A/D-Converter is implemented. Its successive approximation techniqe provides 7 μs conversion time (fOSC=16 MHz). The conversion principle is upward compatible to the one used in the SAB 80C517. The major components are shown in figure 5-1. The comparator is a fully differential comparator for a high power supply rejection ratio and very low offset voltages. The capacitor network is binary weighted providing 10-bit resolution. The table 5-1 below shows the sample time TS and the conversion time TC (including TS), which depend on fOSC and the selected prescaler (see also Bit ADCL in SFR ADCON 1). Table 5-1, ADC-Convertion Time fOSC[MHz] Prescaler fADC[MHz] TS [μs] TC [μs] (incl. TS) 12 ÷ 8 1.5 1.33 8 ÷ 16 0.75 2.8 16 16 ÷ 8 2.0 2.0 7.0 ÷ 16 1.0 4.0 14.0 18 ÷ 8 – – – ÷ 16 1.125 3.555 12.4
Figure 5-1 10-Bit A/D-Converter Semiconductor Group 5 - 4 On-Chip Peripheral Components
Page 1 and 2: Microcomputer Components SAB 80C517
Page 3 and 4: SAB 80C517A/83C517A-5 Revision Hist
Page 5 and 6: 1 Introduction The SAB 80C517A is a
Page 7 and 8: 2 Fundamental Structure The SAB 80C
Page 9 and 10: 3 Memory Organization Semiconductor
Page 11 and 12: 3.2 Data Memory Semiconductor Group
Page 13 and 14: Table 3-1, Special Function Registe
Page 15 and 16: Table 3-1, Special Function Registe
Page 17 and 18: 3.4 Architecture for the XRAM Semic
Page 19 and 20: Figure 3-2 Write Page Address to Po
Page 21 and 22: Figure 3-4 Use of Port 2 as I/O-Por
Page 23 and 24: 3.4.2 Control of XRAM in the SAB 80
Page 25 and 26: EA = 0 EA = 1 XMAP1, XMAP0 XMAP1, X
Page 27 and 28: Table 4-1, Status of all Pins Durin
Page 29 and 30: 4.2 Hardware Power Down Reset Timin
Page 31 and 32: Figure 4-2 Timing Diagram of Leavin
Page 33 and 34: 4.3 Fast internal Reset after Power
Page 35 and 36: Figure 4-4 Power-On of the SAB 80C5
Page 37: Semiconductor Group 5 - 2 On-Chip P
Page 41 and 42: Special Function Register ADDATH, A
Page 43 and 44: 5.3 Additional Compare Mode for the
Page 45 and 46: Special Function Register CC4EN Bit
Page 47 and 48: Semiconductor Group 5 - 12 On-Chip
Page 53 and 54: Special Function Register SRELH, SR
Page 55 and 56: Detailled Description of the Oscill
Page 57 and 58: 6 Interrupt System 6.1 Additional I
Page 59 and 60: Special Function Register IRCON1 Bi
Page 61 and 62: 3.1 Priority Level Structure The fo
Page 63 and 64: 4 Device Specification Device Speci
Page 65 and 66: Logic Symbol Semiconductor Group 7-
Page 67 and 68: Pin Configuration (P-MQFP-100-2) Se
Page 69 and 70: Pin Definitions and Functions (cont
Page 77 and 78: Figure 1 Block Diagram Semiconducto
Page 79 and 80: Semiconductor Group 7-17 Device Spe
Page 85 and 86: s Table 1: Behaviour of P0/P2 and R
Page 89 and 90:
Table 2 Special Function Register (
Page 91 and 92:
Table 3 Special Function Registers
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Table 3 Special Function Registers
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Figure 4 Block Diagram A/D Converte
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Table 4 CCU Compare Configuration S
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Semiconductor Group 7-37 Device Spe
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Figure 6 Block Diagram of Timer 2 S
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Figure 9 Compare-Mode 2 (Port 5 onl
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Figure 10 Interrupt Structure of th
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Figure 10 Interrupt Structure of th
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Table 6 Performing a MDU-Calculatio
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Serial Interface 0 Serial Interface
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Figure 12 Functional Block Diagram
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ALE PSEN Port 0 Port 2 Program Memo
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AC Characteristics (cont’d) Exter
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ROM Verification Characteristics TA
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Application Circuitry for Verifying
Page 137:
Package Outlines Plastic Package, P
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Infineon SAB 80C517A, SAB 83C517A-5 User's Manual ... - Keil

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