ARM Processor Instruction Set
ARM Processor Instruction Set
ARM Processor Instruction Set
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<strong>ARM</strong> <strong>Processor</strong> <strong>Instruction</strong> <strong>Set</strong><br />
5-14<br />
31<br />
MRS<br />
Cond<br />
28<br />
27<br />
23 22<br />
31 28 27<br />
23 22<br />
31<br />
MSR<br />
Cond 00010<br />
MSR<br />
Cond<br />
28<br />
(transfer PSR contents to a register)<br />
21<br />
16<br />
Figure 5-12: PSR transfer<br />
<strong>ARM</strong>7500FE Data Sheet<br />
<strong>ARM</strong> DDI 0077B<br />
Named Partner Open Confidential Access - Preliminary - Preliminary Draft<br />
15<br />
12 11<br />
00010 Ps<br />
001111 Rd<br />
000000000000<br />
(transfer register contents to PSR)<br />
27<br />
00 I 10<br />
23<br />
Pd<br />
22<br />
Pd<br />
21<br />
Destination register<br />
Source PSR<br />
0 = CPSR<br />
1 = SPSR_<br />
Condition field<br />
1010011111 00000000<br />
21 12<br />
1010001111<br />
12 11<br />
Source register<br />
Destination PSR<br />
0 = CPSR<br />
1 = SPSR_<br />
Condition field<br />
(transfer register contents or immediate value to PSR flag bits only)<br />
11<br />
Condition field<br />
4 3<br />
Source operand<br />
Destination PSR<br />
0 = CPSR<br />
1 = SPSR_<br />
Immediate Operand<br />
0 = Source operand is a register<br />
11<br />
Rotate<br />
00000000<br />
shift applied to Imm<br />
Imm<br />
Rm<br />
Rm<br />
1 = Source operand is an immediate value<br />
11 8 7 0<br />
4<br />
Unsigned 8 bit immediate value<br />
3<br />
0<br />
0<br />
0<br />
Source register<br />
0