ARM Processor Instruction Set

Recommendations

Info

ARM Processor Instruction Set 5.8.2 Addressing modes 5-26 The transfer addresses are determined by: • the contents of the base register (Rn) • the pre/post bit (P) • the up/down bit (U) The registers are transferred in the order lowest to highest, so R15 (if in the list) will always be transferred last. The lowest register also gets transferred to/from the lowest memory address. By way of illustration, consider the transfer of R1, R5 and R7 in the case where Rn=0x1000 and write back of the modified base is required (W=1). Figure 5-17: Post-increment addressing, Figure 5-18: Pre-increment addressing, Figure 5-19: Post-decrement addressing, and Figure 5-20: Pre-decrement addressing on page 5-28, show the sequence of register transfers, the addresses used, and the value of Rn after the instruction has completed. In all cases, had write back of the modified base not been required (W=0), Rn would have retained its initial value of 0x1000 unless it was also in the transfer list of a load multiple register instruction, when it would have been overwritten with the loaded value. 5.8.3 Address alignment The address should always be a word aligned quantity. R n 1 R5 R1 3 0x100C 0x1000 0x0FF4 0x100C 0x1000 0x0FF4 4 Figure 5-17: Post-increment addressing ARM7500FE Data Sheet ARM DDI 0077B 0x100C 0x1000 0x0FF4 Named Partner Open Confidential Access - Preliminary - Preliminary Draft Rn R1 2 R7 R5 R1 0x100C 0x1000 0x0FF4
ARM7500FE Data Sheet ARM DDI 0077B Rn Rn 1 R5 R1 3 1 R5 R1 3 ARM Processor Instruction Set 0x100C 0x1000 0x0FF4 0x100C 0x1000 0x0FF4 0x100C 0x1000 0x0FF4 0x100C 0x1000 0x0FF4 Open Access - Preliminary Rn R1 0x100C 0x1000 0x0FF4 Figure 5-18: Pre-increment addressing Rn Figure 5-19: Post-decrement addressing 2 R7 R5 R1 4 R1 2 R7 R5 R1 4 0x100C 0x1000 0x0FF4 0x100C 0x1000 0x0FF4 0x100C 0x1000 0x0FF4 5-27
Page 1 and 2: 5 ARM7500FE Data Sheet ARM DDI 0077
Page 3 and 4: ARM7500FE Data Sheet ARM DDI 0077B
Page 5 and 6: 31 ARM7500FE Data Sheet ARM DDI 007
Page 7 and 8: 5.4.2 Shifts ARM7500FE Data Sheet A
Page 11 and 12: 5.4.4 Writing to R15 ARM7500FE Data
Page 13 and 14: 5.5 PSR Transfer (MRS, MSR) ARM7500
Page 19 and 20: 31 28 5.7.1 Offsets and auto-indexi
Page 23 and 24: 5.7.7 Instruction cycle times 5.7.8
Page 25: 31 28 27 ARM7500FE Data Sheet ARM D
Page 29 and 30: 5.8.6 Inclusion of the base in the
Page 31 and 32: 5.8.11 Examples ARM7500FE Data Shee
Page 33 and 34: 5.9.1 Bytes and words ARM7500FE Dat
Page 37 and 38: 5.12.1 The coprocessor fields ARM75
Page 41 and 42: 5.14 Coprocessor Register Transfers
Page 43 and 44: 5.14.6 Examples ARM7500FE Data Shee
Page 47 and 48: 5.16.4 Loading a word from an unkno

ARM Processor Instruction Set

Create successful ePaper yourself

Delete template?

Save as template?