ARM Processor Instruction Set

ARM Processor Instruction Set
5.13.7 Assembler syntax
5-40
{cond}{L} p#,cd,
LDC load from memory to coprocessor
STC store from coprocessor to memory
{L} when present perform long transfer (N=1), otherwise perform short
transfer (N=0)
{cond} two-character condition mnemonic, see Figure 5-2: Condition codes
on page 5-2
p# the unique number of the required coprocessor
cd is an expression evaluating to a valid coprocessor register number
that is placed in the CRd field
can be:
1 An expression which generates an address:
The assembler will attempt to generate an instruction using the PC as a base
and a corrected immediate offset to address the location given by evaluating
the expression. This will be a PC relative, pre-indexed address. If the address
is out of range, an error will be generated.
2 A pre-indexed addressing specification:
[Rn] offset of zero
[Rn,]{!} offset of bytes
3 A post-indexed addressing specification:
[Rn], offset of bytes
Rn is an expression evaluating to a valid processor register number.
Note, if Rn is R15 then the assembler will subtract 8 from the offset
value to allow for processor pipelining.
{!} write back the base register (set the W bit) if ! is present
5.13.8 Examples
LDC p1,c2,table ;load c2 of coproc 1 from address table,
;using a PC relative address.
STCEQLp2,c3,[R5,#24]! ;conditionally store c3 of coproc 2
;into an address 24 bytes up from R5,
;write this address back to R5, and use
;long transfer
;option (probably to store multiple
;words)
Note: Though the address offset is expressed in bytes, the instruction offset field is in words.
The assembler will adjust the offset appropriately.
ARM7500FE Data Sheet
ARM DDI 0077B
Named Partner Open Confidential Access - Preliminary - Preliminary Draft