ARM Processor Instruction Set

ARM Processor Instruction Set
5.8.2 Addressing modes
5-26
The transfer addresses are determined by:
• the contents of the base register (Rn)
• the pre/post bit (P)
• the up/down bit (U)
The registers are transferred in the order lowest to highest, so R15 (if in the list) will
always be transferred last. The lowest register also gets transferred to/from the lowest
memory address.
By way of illustration, consider the transfer of R1, R5 and R7 in the case where
Rn=0x1000 and write back of the modified base is required (W=1).
Figure 5-17: Post-increment addressing, Figure 5-18: Pre-increment addressing,
Figure 5-19: Post-decrement addressing, and Figure 5-20: Pre-decrement addressing
on page 5-28, show the sequence of register transfers, the addresses used, and the
value of Rn after the instruction has completed.
In all cases, had write back of the modified base not been required (W=0), Rn would
have retained its initial value of 0x1000 unless it was also in the transfer list of a load
multiple register instruction, when it would have been overwritten with the loaded
value.
5.8.3 Address alignment
The address should always be a word aligned quantity.
R n
1
R5
R1
3
0x100C
0x1000
0x0FF4
0x100C
0x1000
0x0FF4
4
Figure 5-17: Post-increment addressing
ARM7500FE Data Sheet
ARM DDI 0077B
0x100C
0x1000
0x0FF4
Named Partner Open Confidential Access - Preliminary - Preliminary Draft
Rn
R1
2
R7
R5
R1
0x100C
0x1000
0x0FF4