ARM Processor Instruction Set

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ARM Processor Instruction Set 5-18 Multiplication by Takes any number greater than or equal to 2^(29) 1S+16I cycles. m is the number of cycles required by the multiply algorithm, which is determined by the contents of Rs The maximum time for any multiply is thus 1S+16I cycles. 5.6.4 Assembler syntax MUL{cond}{S} Rd,Rm,Rs MLA{cond}{S} Rd,Rm,Rs,Rn where: {cond} two-character condition mnemonic, see Figure 5-2: Condition codes on page 5-2 {S} set condition codes if S present Rd, Rm, Rs, Rn are expressions evaluating to a register number other than R15. 5.6.5 Examples MUL R1,R2,R3 ;R1:=R2*R3 MLAEQS R1,R2,R3,R4 ;conditionally ;R1:=R2*R3+R4, ;setting condition codes 5.7 Single Data Transfer (LDR, STR) Table 5-3: Instruction cycle times The instruction is only executed if the condition is true. The various conditions are defined at the beginning of this chapter. The instruction encoding is shown in Figure 5-14: Single data transfer instructions. The single data transfer instructions are used to load or store single bytes or words of data. The memory address used in the transfer is calculated by adding an offset to or subtracting an offset from a base register. The result of this calculation may be written back into the base register if “auto-indexing” is required. ARM7500FE Data Sheet ARM DDI 0077B Named Partner Open Confidential Access - Preliminary - Preliminary Draft
31 28 5.7.1 Offsets and auto-indexing 27 ARM7500FE Data Sheet ARM DDI 0077B 26 25 24 23 22 21 20 19 ARM Processor Instruction Set Cond 01 I P U B W L Rn Rd Offset Open Access - Preliminary 16 15 Figure 5-14: Single data transfer instructions The offset from the base may be either a 12-bit unsigned binary immediate value in the instruction, or a second register (possibly shifted in some way). The offset may be added to (U=1) or subtracted from (U=0) the base register Rn. The offset modification may be performed either before (pre-indexed, P=1) or after (post-indexed, P=0) the base is used as the transfer address. The W bit gives optional auto increment and decrement addressing modes. The modified base value may be written back into the base (W=1), or the old base value may be kept (W=0). 12 11 Source/Destination register Base register Load/Store bit 0 = Store to memory 1 = Load from memory Write-back bit 0 = no write-back 1 = write address into base Byte/Word bit 0 = transfer word quantity 1 = transfer byte quantity Up/Down bit 0 = down; subtract offset from base 1 = up; add offset to base Pre/Post indexing bit 0 = post; add offset after transfer 1 = pre; add offset before transfer Immediate offset 0 = offset is an immediate value 11 Immediate offset Unsigned 12 bit immediate offset 11 1 = offset is a register 4 3 0 shift applied to Rm Condition field Shift Rm 0 0 Offset register 5-19
Page 1 and 2: 5 ARM7500FE Data Sheet ARM DDI 0077
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Page 7 and 8: 5.4.2 Shifts ARM7500FE Data Sheet A
Page 11 and 12: 5.4.4 Writing to R15 ARM7500FE Data
Page 13 and 14: 5.5 PSR Transfer (MRS, MSR) ARM7500
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Page 33 and 34: 5.9.1 Bytes and words ARM7500FE Dat
Page 37 and 38: 5.12.1 The coprocessor fields ARM75
Page 41 and 42: 5.14 Coprocessor Register Transfers
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ARM Processor Instruction Set

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