ARM Processor Instruction Set

ARM7500FE Data Sheet
ARM DDI 0077B
ARM Processor Instruction Set
;enter with numbers in Ra and Rb
;
MOV Rcnt,#1 ;bit to control the division
Div1 CMP Rb,#0x80000000;
;move Rb until greater than Ra
CMPCC Rb,Ra
MOVCC Rb,Rb,ASL#1
MOVCC Rcnt,Rcnt,ASL#1
BCC Div1
MOV Rc,#0
Div2 CMP Ra,Rb ;test for possible subtraction
SUBCS Ra,Ra,Rb ;subtract if ok
ADDCS Rc,Rc,Rcnt;
;put relevant bit into result
MOVS Rcnt,Rcnt,LSR#1;
;shift control bit
MOVNE Rb,Rb,LSR#1;
;halve unless finished
BNE Div2
;
;divide result in Rc
;remainder in Ra
5.16.2 Pseudo random binary sequence generator
It is often necessary to generate (pseudo-) random numbers and the most efficient
algorithms are based on shift generators with exclusive-OR feedback rather like
a cyclic redundancy check generator. Unfortunately the sequence of a 32-bit
generator needs more than one feedback tap to be maximal length (i.e. 2^32-1 cycles
before repetition), so this example uses a 33-bit register with taps at bits 33 and 20.
The basic algorithm is newbit:=bit 33 or bit 20, shift left the 33-bit number and put in
newbit at the bottom; this operation is performed for all the newbits needed
(ie. 32 bits). The entire operation can be done in 5 S cycles:
;enter with seed in Ra (32 bits),
;Rb (1 bit in Rb lsb), uses Rc
;
TST Rb,Rb,LSR#1 ;top bit into carry
MOVS Rc,Ra,RRX ;33 bit rotate right
ADC Rb,Rb,Rb ;carry into lsb of Rb
EOR Rc,Rc,Ra,LSL#12;
;(involved!)
EOR Ra,Rc,Rc,LSR#20;
;(similarly involved!)
;
;new seed in Ra, Rb as before
Open Access - Preliminary
5-45