ARM Processor Instruction Set

ARM7500FE Data Sheet
ARM DDI 0077B
ARM Processor Instruction Set
For example, the following sequence performs a mode change:
MRS R0,CPSR ;take a copy of the CPSR
BIC R0,R0,#0x1F ;clear the mode bits
ORR R0,R0,#new_mode ;select new mode
MSR CPSR,R0 ;write back the modified CPSR
When the aim is simply to change the condition code flags in a PSR, a value can be
written directly to the flag bits without disturbing the control bits. e.g. The following
instruction sets the N,Z,C & V flags:
MSR CPSR_flg,#0xF0000000
;set all the flags regardless of
;their previous state (does not
;affect any control bits)
Note: Do not attempt to write an 8 bit immediate value into the whole PSR since such
an operation cannot preserve the reserved bits.
5.5.3 Instruction cycle times
PSR Transfers take 1 instruction fetch. For more information see 5.17 Instruction
Speed Summary on page 5-47.
5.5.4 Assembler syntax
1 MRS - transfer PSR contents to a register
MRS{cond} Rd,
2 MSR - transfer register contents to PSR
MSR{cond} ,Rm
3 MSR - transfer register contents to PSR flag bits only
MSR{cond} ,Rm
The most significant four bits of the register contents are written to the N,Z,C
& V flags respectively.
4 MSR - transfer immediate value to PSR flag bits only
MSR{cond} ,
The expression should symbolize a 32-bit value of which the most significant
four bits are written to the N,Z,C & V flags respectively.
where:
{cond} two-character condition mnemonic, see Figure 5-2: Condition
codes on page 5-2
Rd and Rm expressions evaluating to a register number other than R15
is CPSR, CPSR_all, SPSR or SPSR_all. (CPSR and
CPSR_all are synonyms as are SPSR and SPSR_all)
is CPSR_flg or SPSR_flg
where used, the assembler will attempt to generate a shifted
immediate 8-bit field to match the expression. If this is
impossible, it will give an error.
Open Access - Preliminary
5-15