ARM Processor Instruction Set

31
28
5.7.1 Offsets and auto-indexing
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ARM7500FE Data Sheet
ARM DDI 0077B
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25
24
23
22
21
20
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ARM Processor Instruction Set
Cond 01 I P U B W L Rn Rd
Offset
Open Access - Preliminary
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15
Figure 5-14: Single data transfer instructions
The offset from the base may be either a 12-bit unsigned binary immediate value in
the instruction, or a second register (possibly shifted in some way). The offset may be
added to (U=1) or subtracted from (U=0) the base register Rn. The offset modification
may be performed either before (pre-indexed, P=1) or after (post-indexed, P=0) the
base is used as the transfer address.
The W bit gives optional auto increment and decrement addressing modes.
The modified base value may be written back into the base (W=1), or the old base
value may be kept (W=0).
12
11
Source/Destination register
Base register
Load/Store bit
0 = Store to memory
1 = Load from memory
Write-back bit
0 = no write-back
1 = write address into base
Byte/Word bit
0 = transfer word quantity
1 = transfer byte quantity
Up/Down bit
0 = down; subtract offset from base
1 = up; add offset to base
Pre/Post indexing bit
0 = post; add offset after transfer
1 = pre; add offset before transfer
Immediate offset
0 = offset is an immediate value
11
Immediate offset
Unsigned 12 bit immediate offset
11
1 = offset is a register
4 3
0
shift applied to Rm
Condition field
Shift Rm
0
0
Offset register
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