13.07.2015 Views

Transparents du cours - VHDL - MAE - Mémoire - Free

Transparents du cours - VHDL - MAE - Mémoire - Free

Transparents du cours - VHDL - MAE - Mémoire - Free

SHOW MORE
SHOW LESS

You also want an ePaper? Increase the reach of your titles

YUMPU automatically turns print PDFs into web optimized ePapers that Google loves.

The Virtex-4 SX platform• Virtex-4 intro<strong>du</strong>ced a new DSP block that had both multiply andaccumulate functionality• For the first time a true “MAC” unit was offered in a Xilinx FPGA.This block was called the DSP48 <strong>du</strong>e to it’s 48-bit output precision• Additional modes of the adder allowed subtract and shift functionsto support scaling of results• Integral registers guarantee high-speed pipelined data-paths formaximum clock frequencyFPGA Intro<strong>du</strong>ction 24© 2009 Xilinx, Inc. All Rights ReservedFor Academic Use Only

Hooray! Your file is uploaded and ready to be published.

Saved successfully!

Ooh no, something went wrong!