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Outils et méthodes de conceptionTest BenchAssertASSERT conditionREPORT string SEVERITY severity level;check_setup: PROCESS (clk, d)BEGINIF (clk’EVENT AND clk=’1’) THEN -- test si front monASSERT d’STABLE(setup_time) -- regarde si d esREPORT "Setup Violation..." -- affiche uSEVERITY WARNING;END IF;END PROCESS check_setup;Bertrand Granado Enseignant-Chercheur (LIP6 / UPMC) Sysprog Hiver 2014 88 / 298
Outils et méthodes de conceptionTest BenchAssertNiveaux de sévérité :Note : utilisé pour information seulement”Note : Chargement de données d’un fichier”Warning : utilisé pour fournir une information sur une erreur en instance”Warning : Détection d’un pic”Error : utilisé pour information seulement”Error : Violation <strong>du</strong> temps d’initialisation”Failure : raporte une grosse erreur”Failure : Ligne RESET instable”Bertrand Granado Enseignant-Chercheur (LIP6 / UPMC) Sysprog Hiver 2014 89 / 298
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SysprogBertrand GranadoEnseignant-C
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Outils et méthodes de conceptionVH
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Outils et méthodes de conceptionDi
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FPGAF.P.G.A et SRAMUtilisation de c
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FPGAStructure d’un F.P.G.ABertran
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FPGAStructure d’un F.P.G.ABertran
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FPGAQu’y a t’il dans un F.P.G.A
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FPGAStructure de l’interconnexion
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FPGAFPGAPrésentation des FPGA comm
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FPGALes FPGA du fabricant AlteraTec
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FPGACyclone IIBertrand Granado Ense
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FPGACyclone II - Logic Element - Mo
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FPGACyclone II - LABBertrand Granad
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FPGACyclone II - LAB - DirectlinkBe
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FPGACyclone II - LAB - WideBertrand
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FPGACyclone II - LAB - Interconnexi
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FPGACyclone II - LAB - HorlogeBertr
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FPGACyclone II - LAB - Mémoire M4K
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FPGACyclone II - LAB - Multiplier i
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FPGACyclone II - Entrées/Sorties -
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FPGALVTTLLow Voltage Transistor Tra
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Stratix III Logic Array Blocks (LAB
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Altera Stratix IIIAdaptive Logic Mo
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Register Packing
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Altera Stratix III, Stratix IVAdapt
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Three Operand AdditionUtilizing Sha
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Register Chain
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Example of Resource Utilization Rep
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Overview• All Xilinx FPGAs contai
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CLBs and SlicesCombinatorial and se
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Look-Up Tables• Combinatorial log
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The SRL16E• The 16 SRAM cells hav
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Outline• Power of Parallelism•
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Multiplier Unit• Embedded 18-bit
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Virtex-4 FeaturesRefer to device da
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The Virtex-4 SX platform• Virtex-
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DSP48 BlockDynamically Programmable
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Virtex-5 FamilyOptimized for logic,
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Virtex-5 ArchitectureEnhanced36Kbit
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DSP48E• Virtex-5SX introduced a f
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Spartan-3Designed for low-cost, hig
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Multiple Domain-optimized Platforms
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Spartan-3A DSP• Incorporates the
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Architecture AlignmentVirtex-6 FPGA
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Higher DSP Performance• Most adva
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Reason 2: FPGAs are ideal for multi
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Reason 4: Lower System Cost through
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The XtremeDSP Slice AdvantageRegReg
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Conception d’un système programm
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