Chapter 24 Multichannel Serial Port Interface (McSPI).

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24.3.1.3.7 Transfer Format With PHA = 0
This section describes the concept of a SPI transmission with the SPI mode0 and the SPI mode2.
In the transfer format with PHA = 0, SPIEN is activated a half cycle of SPICLK ahead of the first SPICLK
edge.
In both master and slave modes, McSPI drives the data lines at the time of SPIEN is asserted.
Each data frame is transmitted starting with the MSB. At the extremity of both SPI data lines, the first bit of
SPI word is valid a half-cycle of SPICLK after the SPIEN assertion.
Therefore, the first edge of the SPICLK line is used by the master to sample the first data bit sent by the
slave. On the same edge, the first data bit sent by the master is sampled by the slave.
On the next SPICLK edge, the received data bit is shifted into the shift register, and a new data bit is
transmitted on the serial data line.
This process continues for a total of pulses on the SPICLK line defined by the SPI word length
programmed in the master device, with data being latched on odd numbered edges and shifted on even
numbered edges.
Figure 24-7 is a timing diagram of a SPI transfer for the SPI mode0 and the SPI mode2, when McSPI is
master or slave, with the frequency of SPICLK equals to the frequency of CLKSPIREF. It should not be
used as a replacement for SPI timing information and requirements detailed in the data manual.
When McSPI is in slave mode, if the SPIEN line is not de-asserted between successive transmissions
then the content of the Transmitter register is not transmitted, instead the last received SPI word is
transmitted.
In master mode, the SPIEN line must be negated and reasserted between each successive SPI word.
This is because the slave select pin freezes the data in its shift register and does not allow it to be altered
if PHA bit equals 0.
In 3-pin mode without using the SPIEN signal, the controller provides the same waveform but with SPIEN
forced to low state. In slave mode SPIEN is useless
SPICLK Edge Nr.
SPICLK (POL=0)
SPICLK (POL=1)
Sample
Data From the Master
Data From the Slave
Slave Select
(SPIEN) (optional)
Figure 24-7. Full Duplex Single Transfer Format with PHA = 0
Begin
End
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
MSB Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 LSB
MSB Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 LSB
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Transfer
SPRUH73E–October 2011–Revised May 2012 Multichannel Serial Port Interface (McSPI)
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