Chapter 24 Multichannel Serial Port Interface (McSPI).
Chapter 24 Multichannel Serial Port Interface (McSPI).
Chapter 24 Multichannel Serial Port Interface (McSPI).
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www.ti.com <strong>McSPI</strong> Registers<br />
Table <strong>24</strong>-14. <strong>McSPI</strong> Interrupt Status Register (MCSPI_IRQSTATUS) Field Descriptions (continued)<br />
Bit Field Value Description<br />
12 TX3_EMPTY Transmitter register is empty or almost empty. This bit indicate FIFO almost full status when<br />
built-in FIFO is used for transmit register (MCSPI_CH3CONF[FFE3W] is set).<br />
Note: Enabling the channel automatically raises this event.<br />
Write 0 Event status bit is unchanged.<br />
Read 0 Event false.<br />
Write 1 Event status bit is reset.<br />
Read 1 Event is pending.<br />
11 Reserved 0 Reads returns 0<br />
10 RX2_FULL Receiver register full or almost full. Channel 2 This bit indicate FIFO almost full status when<br />
built-in FIFO is used for receive register (MCSPI_CH3CONF[FFE2R] is set).<br />
Write 0 Event status bit is unchanged.<br />
Read 0 Event false.<br />
Write 1 Event status bit is reset.<br />
Read 1 Event is pending.<br />
9 TX2_UNDERFLOW Transmitter register underflow. Channel 2<br />
Write 0 Event status bit is unchanged.<br />
Read 0 Event false.<br />
Write 1 Event status bit is reset.<br />
Read 1 Event is pending.<br />
8 TX2_EMPTY Transmitter register empty or almost empty. Channel 2. This bit indicate FIFO almost full<br />
status when built-in FIFO is used for transmit register (MCSPI_CH3CONF[FFE2W] is set).<br />
Write 0 Event status bit is unchanged.<br />
Read 0 Event false.<br />
Write 1 Event status bit is reset.<br />
Read 1 Event is pending.<br />
7 Reserved 0 Reads returns 0<br />
6 RX1_FULL Receiver register full or almost full. Channel 1. This bit indicate FIFO almost full status when<br />
built-in FIFO is use for receive register (MCSPI_CH3CONF[FFE1R] is set).<br />
Write 0 Event status bit is unchanged.<br />
Read 0 Event false.<br />
Write 1 Event status bit is reset.<br />
Read 1 Event is pending.<br />
5 TX1_UNDERFLOW Transmitter register underflow. Channel 1.<br />
Write 0 Event status bit is unchanged.<br />
Read 0 Event false.<br />
Write 1 Event status bit is reset.<br />
Read 1 Event is pending.<br />
4 TX1_EMPTY Transmitter register empty or almost empty. Channel 1. This bit indicate FIFO almost full<br />
status when built-in FIFO is use for transmit register (MCSPI_CH3CONF[FFE1W] is set).<br />
Write 0 Event status bit is unchanged.<br />
Read 0 Event false.<br />
Write 1 Event status bit is reset.<br />
Read 1 Event is pending.<br />
3 RX0_OVERFLOW Receiver register overflow (slave mode only). Channel 0.<br />
Write 0 Event status bit is unchanged.<br />
Read 0 Event false.<br />
Write 1 Event status bit is reset.<br />
Read 1 Event is pending.<br />
SPRUH73E–October 2011–Revised May 2012 <strong>Multichannel</strong> <strong>Serial</strong> <strong>Port</strong> <strong>Interface</strong> (<strong>McSPI</strong>)<br />
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