Chapter 24 Multichannel Serial Port Interface (McSPI).

www.ti.com Functional Description
24.3.2.10.5 Multiple SPI Word Access
The CPU has the ability to perform multiple SPI word access to the receive or transmit registers within a
single 32-bit OCP access by setting the bit field MCSPI_MODULCTRL[MOA] to ‘1’ under specific
conditions:
• The channel selected has the FIFO enable.
• Only FIFO sense enabled support the kind of access.
• The bit field MCSPI_MODULCTRL[MOA] is set to 1
• Only 32-bit OCP access and data width can be performed to receive or transmit registers, for other
kind of access the CPU must de-assert MCSPI_MODULCTRL[MOA] bit fields.
• The Level MCSPI_XFERLEVEL[AEL] and MCSPI_XFERLEVEL[AFL] must be 32-bit aligned , it means
that AEL[0] = AEL[1] = 1 or AFL[0] = AFL[1] = 1.
• If MCSPI_XFERLEVEL[WCNT] is used it must be configured according to SPI word length.
• The word length of SPI words allows to perform multiple SPI access, that means that
MCSPI_CH(I)CONF[WL] < 16
Number of SPI word access depending on SPI word length:
• 3 ≤ WL ≤ 7, SPI word length smaller or equal to byte length, four SPI words accessed per 32-bit OCP
read/write. If word count is used (MCSPI_XFERLEVEL[WCNT]), set the bit field to
WCNT[0]=WCNT[1]=0
• 8 ≤ WL ≤ 15, SPI word length greater than byte or equal to 16-bit length, two SPI words accessed per
32-bit OCP read/write. If word count is used (MCSPI_XFERLEVEL[WCNT]), set the bit field to
WCNT[0]= 0.
• 16 ≤ WL multiple SPI word access not applicable.
24.3.2.11 First SPI Word Delayed
The McSpi controller has the ability to delay the first SPI word transfer to give time for system to complete
some parallel processes or fill the FIFO in order to improve transfer bandwidth. This delay is applied only
on first SPI word after SPI channel enabled and first write in Transmit register. It is based on output clock
frequency.
This option is meaningful in master mode and single channel mode MCSPI_MODULECTRL[SINGLE]
asserted.
SPI Shift Clock
(Module Generated
Internal Clock)
Channel Enabled
(OCP Domain)
Internal Start Request
(SPI Domain)
SPICLKO
(POL=0)
SPIENO
Figure 24-21. Master Single Channel Initial Delay
Initial Delay on First SPI
Word (INITDLY Value)
Few delay values are available: No delay, 4/8/16/32 Spi cycles.
Its accuracy is half cycle in clock bypass mode and depends on clock polarity and phase.
SPRUH73E–October 2011–Revised May 2012 Multichannel Serial Port Interface (McSPI)
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