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Chapter 24 Multichannel Serial Port Interface (McSPI).

Chapter 24 Multichannel Serial Port Interface (McSPI).

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www.ti.com Functional Description<br />

<strong>24</strong>.3.2.10.2 Buffer Almost Full<br />

The bit field MCSPI_XFERLEVEL[AFL] is needed when the buffer is used to receive SPI word from a<br />

slave (MCSPI_CH(I)CONF[FFER] must be set to 1) and register width depends on the generic parameter<br />

FFNBYTE value. It defines the almost full buffer status.<br />

When FIFO pointer reaches this level an interrupt or a DMA request is sent to the CPU to enable system<br />

to read AFL+1 bytes from receive register. Be careful AFL+1 must correspond to a multiple value of<br />

MCSPI_CH(I)CONF[WL].<br />

When DMA is used, the request is de-asserted after the first receive register read.<br />

No new request will be asserted until the system has performed the correct number of read operations<br />

from the buffer.<br />

LH or DMA Read<br />

.<br />

Core Write<br />

Full<br />

Empty<br />

*<br />

Figure <strong>24</strong>-19. Buffer Almost Full Level (AFL)<br />

* non-DMA mode only. In DMA mode, the DMA RX request is asserted<br />

to its active level under identical conditions.<br />

<br />

(in bytes)<br />

NOTE: SPI_IRQSTATUS register bits are not available in DMA mode. In DMA mode, the<br />

SPIm_DMA_RXn request is asserted on the same conditions as the SPI_IRQSTATUS<br />

RXn_FULL flag.<br />

SPRUH73E–October 2011–Revised May 2012 <strong>Multichannel</strong> <strong>Serial</strong> <strong>Port</strong> <strong>Interface</strong> (<strong>McSPI</strong>)<br />

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Copyright © 2011–2012, Texas Instruments Incorporated<br />

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