Chapter 24 Multichannel Serial Port Interface (McSPI).

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www.ti.com McSPI Registers 24.5.1.3 McSPI System Status Register (MCSPI_SYSSTATUS) The McSPI system status register (MCSPI_SYSSTATUS) provides status information about the module excluding the interrupt status information. The MCSPI_SYSSTATUS is shown in Figure 24-28 and described in Table 24-13. Figure 24-28. McSPI System Status Register (MCSPI_SYSSTATUS) 31 16 Reserved 15 1 0 LEGEND: R = Read only; -n = value after reset R-0 Reserved RESETDONE R-0 R-0 Table 24-13. McSPI System Status Register (MCSPI_SYSSTATUS) Field Descriptions Bit Field Value Description 31-1 Reserved 0 Reserved for module specific status information. Read returns 0. 0 RESETDONE Internal Reset Monitoring 0 Internal module reset is on-going 1 Reset completed SPRUH73E–October 2011–Revised May 2012 Multichannel Serial Port Interface (McSPI) Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated 4163
McSPI Registers www.ti.com 24.5.1.4 McSPI Interrupt Status Register (MCSPI_IRQSTATUS) The McSPI interrupt status register (MCSPI_IRQSTATUS) regroups all the status of the module internal events that can generate an interrupt. The MCSPI_IRQSTATUS is shown in Figure 24-29 and described in Table 24-14. NOTE: In SYSTEST mode, the bits of this register have no meaning and always read 0. Figure 24-29. McSPI Interrupt Status Register (MCSPI_IRQSTATUS) 31 18 17 16 Reserved EOW Rsvd R/W-0 R/W-0 R-0 15 14 13 12 11 10 9 8 Rsvd RX3_FULL TX3_UNDERFLOW TX3_EMPTY Reserved RX2_FULL TX2_UNDERFLOW TX2_EMPTY R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 7 6 5 4 3 2 1 0 Rsvd RX1_FULL TX1_UNDERFLOW TX1_EMPTY RX0_OVERFLOW RX0_FULL TX0_UNDERFLOW TX0_EMPTY R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; -n = value after reset Table 24-14. McSPI Interrupt Status Register (MCSPI_IRQSTATUS) Field Descriptions Bit Field Value Description 31-18 Reserved 0 Reads returns 0 17 EOW End of word (EOW) count event when a channel is enabled using the FIFO buffer and the channel has sent the number of McSPI words defined by the MCSPI_XFERLEVEL[WCNT]. Write 0 Event status bit is unchanged. Read 0 Event false. Write 1 Event status bit is reset. Read 1 Event is pending. 16 Reserved 0 Reserved 15 Reserved 0 Reads returns 0 14 RX3_FULL Receiver register is full or almost full. Only when Channel 3 is enabled. This bit indicate FIFO almost full status when built-in FIFO is used for receive register (MCSPI_CH3CONF[FFE3R] is set). Write 0 Event status bit is unchanged. Read 0 Event false. Write 1 Event status bit is reset. Read 1 Event is pending. 13 TX3_UNDERFLOW Transmitter register underflow. Only when Channel 3 is enabled. The transmitter register is empty (not updated by Host or DMA with new data) before its time slot assignment. Exception: No TX_underflow event when no data has been loaded into the transmitter register since channel has been enabled. Write 0 Event status bit is unchanged. Read 0 Event false. Write 1 Event status bit is reset. Read 1 Event is pending. 4164 Multichannel Serial Port Interface (McSPI) SPRUH73E–October 2011–Revised May 2012 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated
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Chapter 24 Multichannel Serial Port Interface (McSPI).

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