Chapter 24 Multichannel Serial Port Interface (McSPI).
Chapter 24 Multichannel Serial Port Interface (McSPI).
Chapter 24 Multichannel Serial Port Interface (McSPI).
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<strong>24</strong>.2.1 <strong>McSPI</strong> Connectivity Attributes<br />
The general connectivity attributes for the <strong>McSPI</strong> module are shown in Table <strong>24</strong>-2.<br />
Table <strong>24</strong>-2. <strong>McSPI</strong> Connectivity Attributes<br />
Attributes Type<br />
Power Domain Peripheral Domain<br />
Clock Domain PD_PER_L4LS_GCLK (<strong>Interface</strong>/OCP)<br />
PD_PER_SPI_GCLK (Func)<br />
Reset Signals PER_DOM_RST_N<br />
Idle/Wakeup Signals Smart Idle<br />
Interrupt Requests 1 interrupt to MPU subsystem and PRU-ICSS (<strong>McSPI</strong>0INT)<br />
1 interrupt to MPU subsystem only (<strong>McSPI</strong>1INT)<br />
DMA Requests 4 DMA requests per instance to EDMA<br />
• 1 RX request for CS0 (SPIREVT0)<br />
• 1 TX request for CS0 (SPIXEVT0)<br />
• 1 RX request for CS1 (SPIREVT1)<br />
• 1 TX request for CS1 (SPIXEVT1)<br />
Physical Address L4 Peripheral slave port<br />
<strong>24</strong>.2.2 <strong>McSPI</strong> Clock and Reset Management<br />
The SPI module clocks can be woken up in two manners: by the SPI module itself using the SWAKEUP<br />
signal (refer to the module functional spec for detailed conditions), or directly from an external SPI master<br />
device by detecting an active low level on its chip select input pin (CS0n) using a GPIO attached to that<br />
device pin. Neither of these methods is supported on the device.<br />
Table <strong>24</strong>-3. <strong>McSPI</strong> Clock Signals<br />
Clock Signal Max Freq Reference / Source Comments<br />
CLK 100 MHz CORE_CLKOUTM4 / 2 pd_per_l4ls_gclk<br />
<strong>Interface</strong> clock From PRCM<br />
CLKSPIREF 48 MHz PER_CLKOUTM2 / 4 pd_per_spi_gclk<br />
Functional clock From PRCM<br />
<strong>24</strong>.2.3 <strong>McSPI</strong> Pin List<br />
The <strong>McSPI</strong> interface pins are summarized in Table <strong>24</strong>-4.<br />
Table <strong>24</strong>-4. <strong>McSPI</strong> Pin List<br />
Pin Type Description<br />
SPIx_SCLK I/O SPI serial clock (output when master,<br />
input when slave)<br />
SPIx_D0 I/O Can be configured as either input or<br />
output (MOSI or MISO)<br />
SPIx_D1 I/O Can be configured as either input or<br />
output (MOSI or MISO)<br />
SPIx_CS0 I/O SPI chip select 0 output when master,<br />
input when slave (active low)<br />
SPIx_CS1 O SPI chip select 1 output when master,<br />
input when slave (active low)<br />
SPRUH73E–October 2011–Revised May 2012 <strong>Multichannel</strong> <strong>Serial</strong> <strong>Port</strong> <strong>Interface</strong> (<strong>McSPI</strong>)<br />
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