Design and Implementation of TinyGALS: A Programming Model for ...

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Module definition for leds. include components{ INT_TO_LEDS; }; init{ INT_TO_LEDS:init; }; ports in{ leds_in; }; ports out{ }; leds_in INT_TO_LEDS:fire Figure 5: The definition of the leds module shown in Figure 1. 2.2.3 TinyGALS Application At the top level of a TinyGALS program, modules are connected to form a complete application. A TinyGALS application A is a 5-tuple: A = (MODULESA,GLOBALSA,VARMAPSA,CONNECT IONSA,STARTA), (3) where MODULESA is a list of modules in the application; GLOBALSA is a set of global variables; VARMAPSA is a set of mappings, each of which maps a global variable to a parameter (in PARAMET ERSMi ) of a module in MODULESA 6 ; CONNECT IONSA is a set of the connections between module output ports and input ports; STARTA is the name of an input port of exactly one module in the application. Section 2.3.4 describes which configurations of modules within an application are valid. Figure 6 shows the code for defining the application shown in Figure 1. The application contains two modules, count and leds. The output port count_out of module count is connected to the input port leds_in of module leds. The definition declares that the connection between count_out and leds_in has a FIFO queue of size 50. The last 6 Refer to information on TinyGUYS in Section 2.4. 12
Application definition. include modules{ count; leds; }; count_out -> leds_in 50 START@ count_start Figure 6: Definition of the application shown in Figure 1. line in the definition says that the system start port is count_start. Note that arguments (initial data) may be passed to the system start port on the same line. Using the tuple notation given in Equation 3, the example application can be defined as 2.3 TinyGALS Semantics A = (MODULESA = [count,leds], GLOBALSA = /0, VARMAPSA = /0, CONNECT IONSA = [(count out,leds in)], STARTA = count start). In this section, we discuss the semantics of execution within a component, between components within a module, and between modules within an application. We also include a discussion of the conditions for well-formedness an application. 2.3.1 Assumptions The TinyGALS architecture is intended for a platform with a single processor. All memory is statically allocated; there is no dynamic memory allocation. A TinyGALS program 13
Page 1: Design and Implementation of TinyGA
Page 5 and 6: Contents 1 Introduction 1 2 The Tin
Page 7: 8 Acknowledgements 60 iii
Page 10 and 11: does not require synchronization, w
Page 12 and 13: integrate subsystems that share a c
Page 14 and 15: 2 The TinyGALS Programming Model Ti
Page 16 and 17: 2.2.1 TinyGALS Components Component
Page 18 and 19: Component implementation for COUNTE
Page 22 and 23: uns in a single thread of execution
Page 24 and 25: as in a normal method call. 8 The g
Page 26 and 27: nondeterministic component firing o
Page 28 and 29: module. Tokens are placed in input
Page 30 and 31: Application def. include modules{ A
Page 32 and 33: 1. The values of all internal varia
Page 34 and 35: Conditions for well-formedness Here
Page 36 and 37: Determinacy of a system without glo
Page 38 and 39: I0 q0 I1 I2 In a 1 0,0 a 1 0,0 + a2
Page 40 and 41: app_init() app_start() statevar_PAR
Page 42 and 43: the same name as the output port. T
Page 44 and 45: if there is an event in the global
Page 46 and 47: 5 Example The TinyGALS programming
Page 48 and 49: the motes as three separate modules
Page 50 and 51: Table 4: Code size comparison of BL
Page 52 and 53: gered modules in TinyGALS and tasks
Page 54 and 55: critical section to maintain data i
Page 56 and 57: and a pull port is illegal. Every p
Page 58 and 59: Poll packet from receive DMA ring P
Page 60 and 61: Click router thread TinyGALS thread
Page 62 and 63: unlike Click, the TinyGALS model do
Page 64 and 65: 6.5 Timed Multitasking Timed multit
Page 66 and 67: quiescent system state to the next
Page 68 and 69: 8 Acknowledgements I wish to thank
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[11] S. S. Bhattacharyya, E. Cheong
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[31] T. J. Mowbray, W. A. Ruh, and
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